JPH0380728A - Frame synchronization transmission timing system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a frame synchronization transmission timing method in an uplink and downlink full-duplex transmission/reception system in which the timing for transmitting an uplink transmission data frame with respect to a downlink reception data frame is specified. The purpose of this is to make the hardware configuration of the machine economical and to obtain accurate transmission timing, and the timing for sending out uplink transmission data frames relative to downlink reception data frames is specified. In the full-duplex transmission/reception system, a downlink data receiving means receives downlink data, a reception processing section performs reception processing based on a reception request when data is received by the downlink data reception means, and a reception processing section receives data from the reception processing section. a frame opening detection section that detects a frame synchronization pattern from data; and bits of received data based on a detection signal of the frame synchronization pattern from the frame synchronization detection section and a bit count request that is a notification from the downlink data receiving means. a control means that implements in firmware a bit count processing unit that counts and sends a transmission timing notification when a predetermined count value is reached; and a transmission processing unit that performs data transmission processing based on the transmission timing notification;
and upstream data transmitting means for transmitting data to be transmitted from the I control means as upstream transmission data.

[Industrial application field]

The present invention relates to a frame-synchronized transmission timing method, and more particularly to a frame-synchronized transmission timing method in an uplink/downstream full-duplex transmission/reception system in which the timing for transmitting an uplink transmission data frame with respect to a downlink reception data frame is specified. .

In the above-mentioned up-down and down-duplex full-duplex transmission/reception system, in a simple car telephone system consisting of one base station and a plurality of mobile stations, the base station The timing for transmitting an uplink data frame from a mobile station relative to a downlink data frame from a mobile station is defined.

Conventionally, this frame synchronization transmission timing means has been implemented in hardware in mobile stations, but it is required to make mobile stations more economical and inexpensive in order to popularize simple car telephone systems. Therefore, the frame synchronization transmission timing means described above also needs to have a more economical configuration.

Furthermore, regarding transmission timing, it is desired to improve reliability by obtaining accurate timing with few errors.

(Prior Art) FIG. 5 shows a configuration diagram of an example of a conventional frame synchronous transmission timing system. FIG. 5 shows the configuration of a mobile station when applied to the simple car phone system,
Downlink reception data from the base station is serially received by the reception frame 8-bit data reception means 51 and the reception frame 1-bit data reception means 52. The above received data is composed of frames, and the received frame 8-bit data receiving means 51 converts this received data into serial and parallel data.
The bit parallel data is supplied to frame synchronization detection means 53 and control means 54, respectively.

On the other hand, the received frame 1-bit data receiving means 52 receives the above received data bit by bit and inputs the bit counter 5.
Supply to 5. This bit counter 55 is set by the detection signal output from the frame synchronization detection means 53 when a fixed pattern of 8-bit frame synchronization pattern is detected by the frame synchronization detection means 53, and at this point, the transmission timing notification is controlled. to the means 54.

The control means 54 controls the reception frame 8-bit data reception means 5.
When 8-bit data from 1 is input, control means 5
The reception processing unit 56 in 4 is notified of the existence of the received data and requests processing of the received data. On the other hand, when the operator of the mobile station performs transmission, the transmission processing section 57 issues a transmission request to the control means 54, and the transmission data is transferred based on a transmission timing notification from the control means 54. This reception processing section 56 and transmission processing section 57
is realized by firmware processing by the control means 54 using a microprocessor.

The 8-bit data for transmission taken out from the control means 54 is converted into a predetermined frame format by the transmission frame data sending means 59 and serially transmitted to the base station as transmission data.

As described above, according to this conventional example, the frame synchronization means 5
3 and a bit counter 55 are configured by hardware, and the firmware directly performs reception processing in response to a reception request.For transmission, a transmission timing notification is received from the hardware, and transmission is performed immediately after the frame synchronization signal is detected. Performs transmission processing to send data frames.

Further, FIG. 6 shows another configuration diagram of the conventional frame synchronization transmission timing system. In the figure, the same components as those in FIG. 5 are denoted by the same reference numerals, and the explanation thereof will be omitted. In FIG. 6, when there is received data, the control means 61 issues a reception request to the reception processing section 62 in the control means 61. Upon receiving this, the reception processing section 62 transfers the received data to the frame synchronization detection section 63.

When the frame synchronization detection section 63 detects a fixed pattern frame synchronization signal from the received data, the timer processing section 64
Set the timer and start timer processing. Thereafter, the timer processing section 64 sends the transmission timing notification generated by itself to the transmission processing section 65 at one frame cycle. The transmission processing section 65 issues a transmission request to the control means 61 based on this transmission timing notification.

In this conventional example, not only the reception processing section 62 and the transmission processing section 65 but also the frame synchronization detection section 63 and the timer processing section 64 are configured by firmware processing using a microprocessor by the control means 54. Once the timer is set, it will automatically notify the transmission timing from then on, so even if there is a data error due to fading,
The feature is that the transmission timing can be obtained.

[Problem to be solved by the invention]

However, in the conventional system shown in FIG. 5, the frame synchronization means 53 and the bit counter 55 are constructed of complicated hardware circuits, so the circuit scale is large and the cost of the device is high. Furthermore, since only a fixed transmission timing can be obtained if the system is developed to a certain degree, it also has the disadvantage that it cannot support other types of transmission timing.

Further, the conventional method shown in FIG. 6 includes a frame synchronization detection section 63 and a timer processing section 64 for obtaining transmission timing.
This is done in firmware, so it has a simple hardware configuration, but since there is a time error in the clock processing by the software timer, the actual downstream received data frame may not be accurate. There is a drawback that synchronization cannot be achieved and errors occur.

The present invention has been made in view of the above points, and it is an object of the present invention to provide a frame synchronization transmission timing method that can make the hardware configuration of the handset side economical and obtain accurate transmission timing. .

[Means to solve the problem]

FIG. 1 shows a basic configuration diagram of the present invention. In the figure, 11 is a downlink data receiving means that receives downlink data. 12 is a control means, which includes a reception processing section 13. Frame opening detection unit 14
．． It has a bit count processing section 15 and a transmission processing section 16, and these are realized by firmware.

Here, the above-mentioned reception processing section 13 is the downlink data receiving means 1
The received data is processed based on the reception request at the time of data reception in step 1. The frame synchronization detection unit 14 detects a frame synchronization pattern from the received data.

The bit count processing unit 15 counts the bits of the received data based on the frame synchronization pattern detection signal and the bit count request that is the notification from the downlink data receiving means 11, and issues a transmission timing notification when a predetermined count value is reached. Send.

The transmission processing unit 16 performs data transmission processing based on the above-mentioned transmission timing notification. Further, the uplink data transmitting means 17 transmits the data to be transmitted from the control means 12 as uplink transmission data.

[Effect]

In the present invention, when the frame synchronization detection section 14 detects a frame synchronization pattern, the bit count processing section 15 counts the bits of the received data, and when a predetermined count value is reached, the firmware specifies that a transmission timing notification is performed. It is distinctive in that it is realized by

As a result, the hardware configuration is as follows:
1 and upstream data transmitting means 17, the hardware configuration can be simplified compared to the conventional system shown in FIG.

Furthermore, since the present invention performs bit counting of received data instead of timer processing, it is possible to prevent errors in transmission timing due to accumulation of time errors caused by timer processing as in the conventional method shown in FIG. 6. I can do it.

〔Example〕

FIG. 2 shows a configuration diagram of an embodiment of the system of the present invention.

In the figure, the same components as in FIG. 1 are given the same reference numerals. The embodiment shown in FIG. 2 shows the main part of the configuration of the mobile station of the above-described simple car telephone system, in which downlink received data from a base station (not shown) is sent to an 8-bit data receiving circuit 21 and a 1-bit reception detecting circuit. 22, respectively. The 8-bit data receiving circuit 21 converts input received data into serial and parallel data, inputs the 8-bit parallel data to an 8-bit general-purpose microprocessor (hereinafter simply referred to as microprocessor) 23, and also sends an 8-bit reception interrupt notification to the microprocessor. This is done for the processor 23.

On the other hand, the 1-bit reception detection circuit 22 notifies the microprocessor 23 of a 1-bit reception interrupt every time it detects 1 bit of received data.

In this embodiment, the hardware configuration of this embodiment is such that the 1-bit reception detection circuit 22 issues an interrupt request to the microprocessor 23 to notify only that received data has been received for each bit. This is the above feature.

The microprocessor 23 has read-only memory (R
OM) 24 and random access memory (RAM)
Together with .25, it constitutes the control means 12, and these constitute the reception processing section 13.25. Frame synchronization detection unit 14. Bit count processing unit 11 15 and transmission processing unit 1
6 is realized through firmware processing. Furthermore, the microprocessor 23 supplies the data to be transmitted 8 bits at a time in parallel to the 8-bit transmission circuit 26, where it is converted from parallel to serial, and the transmission data in a predetermined format is serially output to a modem (not shown). do.

Next, the operations of the frame synchronization detection section 14 and the bit count processing section 15 will be explained with reference to the flowchart of FIG. 3 and the transmission timing explanatory diagram of FIG. 4.

In FIG. 3, the first two steps 101 and 102
indicates the firmware processing by the frame synchronization detection section 14, and the remaining steps 103 to 117 indicate the firmware processing by the bit count processing section 15.

First, in step 101, it is detected whether or not a fixed frame synchronization pattern exists from the received data, and if so, it is determined whether or not the frame synchronization pattern has been detected in two consecutive frames.

When a frame synchronization pattern is detected in two consecutive frames, the bit count processing section 15 moves to firmware processing, and first, in step 103, the bit counter is counted down by 8 bits each time the 8-bit parallel received data is input. ), then it is determined whether the counted value is the value immediately before the end of counting for one frame (step 104).

Here, for example, in the case where the data bit length per frame of downlink received data is 240 bits, and the timing for transmitting the transmission frame data is specified to be synchronized immediately after the frame synchronization pattern of the downlink received data frame. explain. In addition, the format of one frame of downlink received data is as shown in FIG. 4(A), in which a fixed pattern of bit sync BS, a fixed pattern of frame synchronization pattern FS, and data DATA are synthesized in chronological order. It is assumed that both BS and FS have a bit length that is an integral multiple of 8 bits.

Microprocessor 23 (bit count processing unit 15)
The bit counter is counted down every 8 bits from 240 bits in step 103, and then in step 104.
The value of the bit counter is la just before the end of one frame.
(For example, "4"), in step 105 the 1-bit reception interrupt notification IRQ is enabled, and in the following step 106 the 1-bit reception detection circuit 22
The process is switched to count down the bit counter every time 1-bit received data is input. In this way, in this embodiment, the 1-bit reception interrupt notification IRQ is normally masked and enabled only at the minimum necessary time, thereby eliminating unnecessary load on the microprocessor 23 and reducing the burden on the microprocessor 23. This minimizes the decline in the processing capacity of the Set+J23.

Next, in step 107, it is determined whether or not the bit counter has finished counting for one frame based on whether the count value is "0". If not, step 106
Return to “O” and continue counting down one bit at a time.
When it reaches step 108, the 1-bit reception interrupt notification IRQ is masked again, and then the process goes to step 109, where the countdown process is switched again to every 8 bits.
Performs rounding of the total counter. This rounding process is
This is a process of presetting the bit counter to the value "236" obtained by subtracting "4" from "240".

The above is the processing when there is no transmission request. Next, the processing when there is a transmission request will be explained.

Following the rounding of the bit counter in step 109 above, the bit counter is set to "236" in step 110.
8 bits are counted down from then, and in step 111 it is determined whether the count has reached the value "4" immediately before the end of counting for one frame. If not, the process returns to step 110.

In this way, the 8-bit parallel received data is generated as shown in Figure 4 (
As shown schematically in Figure C), each time the bit counter is inputted, the value of the bit counter is counted down by 8 bits as shown in Figure 11 (D), and when the 11 value reaches "4",
The 1-bit reception interrupt notification IRQ is enabled (EN) as schematically shown in step 112 of FIG. 3).
Each time the bit counter receives one bit of received data,
As shown in (B) and (D) of the same figure, the countdown is performed by "1" until the count value reaches "011" (step 11).
s; 114).

When the count value is "0", it is the first 1 bit position of the data DATA immediately after the frame friend pattern FS, and at this time, as schematically shown in FIG. 4(B), the 1 bit reception interrupt notification IRQ is Mask again step 11 in Figure 3.
5) Start the transmission process as the transmission timing,
Step 116), the same rounding of the bit counter as in step 109 is performed (step 111>).
As schematically shown in E), the sub-value of the bit counter “O
Transmission frame data is transmitted from the time It. When the bit counter fraction processing in step 117 is completed, the process returns to step 110 and starts counting down by 8 bits.

In this way, according to this embodiment, the bit counter is counted down every time received data is input, and when the 1 value is "
Since the transmission timing is notified at the time of turning on, there is no shift in transmission timing due to time errors such as timer processing, and accurate transmission timing can be notified.

Furthermore, according to the present embodiment, a 1-bit reception notification is bit-counted by sending an interrupt notification to the microprocessor 23, but what if interrupts are always accepted? microprocessor 23
Since the processing capacity of the microprocessor 23 decreases, an unnecessary load on the microprocessor 23 is avoided by accepting 1-bit reception interrupt notifications only when necessary.

Note that the present invention is not limited to the above-described embodiments, but can be widely applied to mobile stations in a mobile communication system that includes a 1:N base station and a mobile station.

(Effects of the Invention) As described above, according to the present invention, the hardware configuration can be simplified, so the circuit size can be reduced and the cost of the device can be reduced, and transmission can be performed by counting bits of received data instead of by soft timer processing. Since timing notification is performed, accurate transmission timing notification can be performed, and furthermore, transmission timing notification can be variably set, so it has features such as being advantageous when applied to other mobile communication systems. It is something.

[Brief explanation of drawings]

Fig. 1 is a diagram of the principle configuration of the present invention, Fig. 2 is a block diagram of an embodiment of the invention, Fig. 3 is a flowchart for explaining the operation of an embodiment of the main part of the invention, and Fig. 4 is a bit counter. FIG. 5 is a configuration diagram of an example of the conventional system, and FIG. 6 is a configuration diagram of another example of the conventional system. In the figure, 11 is a downlink data receiving means, 12 is a control means, 13 is a reception processing unit, 14 is a frame synchronization detection unit, 15 is a bit count processing unit, 16 is a transmission processing unit, 17 is an uplink data transmission unit, and 21 is a An 8-bit data receiving circuit, 22 a 1-bit reception detection circuit, and 23 an 8-bit general-purpose microprocessor.

Claims (1)

[Scope of Claims] In an uplink and downlink full-duplex transmission/reception system in which the timing for transmitting an uplink transmission data frame with respect to a downlink reception data frame is defined, a downlink data receiving means for receiving downlink data. (11), a reception processing unit (13) that performs reception processing based on a reception request when receiving data by the downlink data reception means (11), and a reception processing unit (13) that extracts a frame synchronization pattern from the received data from the reception processing unit (13). A frame synchronization detector (14) to detect, a detection signal of the frame synchronization pattern from the frame synchronization detector (14), and the downlink data receiving means (11).
A bit count processing unit (bit count processing unit) that counts bits of received data based on a bit count request that is a notification from
15), and a transmission processing unit (16) that performs data transmission processing based on the transmission timing notification, using firmware. A frame synchronized transmission timing system, comprising: upstream data transmission means (17) for transmitting as transmission data.