JPH0382080A - Bipolar type semiconductor switching device - Google Patents

Bipolar type semiconductor switching device

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Publication number
JPH0382080A
JPH0382080A JP21963289A JP21963289A JPH0382080A JP H0382080 A JPH0382080 A JP H0382080A JP 21963289 A JP21963289 A JP 21963289A JP 21963289 A JP21963289 A JP 21963289A JP H0382080 A JPH0382080 A JP H0382080A
Authority
JP
Japan
Prior art keywords
gate
electrode
leading
main
buried gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21963289A
Other languages
Japanese (ja)
Inventor
Tadakuro Minato
忠玄 湊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP21963289A priority Critical patent/JPH0382080A/en
Publication of JPH0382080A publication Critical patent/JPH0382080A/en
Pending legal-status Critical Current

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  • Thyristors (AREA)

Abstract

PURPOSE:To facilitate leading of a buried gate electrode and to simultaneously obtain a large capacity device having high electrical and mechanical long-term reliability accurately and easily by forming the leading of a buried gate substantially on the same plane as that of at least one main electrode formed in a mesa shape. CONSTITUTION:In a bipolar type semiconductor switching device in which first and second main electrodes 7, 8 are formed on both main surfaces through semiconductor substrates 1, 2 to become main current paths, and having buried gate electrode regions 3, 4 for controlling ON, OFF of a main current in the substrates near at least one main electrode, the leading 19 of the buried gate is formed substantially in the same plane as that of at least one electrode 8 formed in a mesa shape. For example, second gate leading protrusions 18 are formed on both buried gate type static induction thyristors, second gate leading electrode wirings 19 covering the whole part is provided, and second gate leading electrode wiring 19 is formed simultaneously in the same step, material and thickness as those of anode electrode wirings 8.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明はバイポーラ型半導体スイッチング素子の構造
に関し、特にGTOサイリスク、 SIサイリスタ等の
高速大容量素子のゲート電極構造に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of bipolar semiconductor switching elements, and particularly to the gate electrode structure of high-speed, large-capacity elements such as GTO thyristors and SI thyristors.

〔従来の技術〕[Conventional technology]

従来のものの例として両面埋込ゲート型静電誘導サイリ
スタ(以下Buried−Gate type DQu
ble GateStatic Inductioth
 Thyristorの一部ととってDG−3IThと
略す)を説明する。当社において試作したDG−8IT
h (Proceedings of 1988 In
terrationalSymposinrn on 
Pmer Semt conductor Deviu
s 、 Tokyo。
An example of a conventional type is a double-sided buried gate type electrostatic induction thyristor (hereinafter referred to as Buried-Gate type DQu).
ble GateStatic Induction
DG-3ITh, which is a part of Thyristor, will be explained. DG-8IT prototyped by our company
h (Proceedings of 1988 In
terrationalSymposinrn on
Pmer Semt conductor Deviu
s, Tokyo.

pp、 183〜188 r A Dou)cue −
Gate −Type 5tatic −tnduct
ionThyristor J )に示された断面模式
図を第4図に示す。
pp, 183-188 r A Dou) cue -
Gate-Type 5tatic-tndduct
ionThyristor J) is shown in FIG. 4.

図において(1)はN高比抵抗半導体基板、(2)はp
高比抵抗半導体基板で、この中に各々反灯導電型の第1
.第2ゲート領域+3+ 、 +41があり、カソード
+ N低抵抗領域(5)とアノードP低抵抗頗域(6)の間
を流れる主電流のオン・オフを制御する。+7) 18
+ +9) tl(Dは咎々カソード、アノード、第1
ゲート、第2ゲート部の電極配線、antizはアノー
ド(6)−力ソード(5)間を流れる主電流の通路とな
る高比抵抗チャネル明域、(13は素子の機械的補強と
辷−トシンクを兼ねた陽極Mo板で、第2ゲート電極配
線αGの取り111 L、部分の中央のゲート部Mai
ll (14は、絶縁用セラミックシールα9で絶縁さ
れ、同じく素子周辺部のMo部もU■の絶縁用セラミッ
クで絶縁する。07)はPN接合がglHしている素子
周辺部の機械的−電気的安定化のためにStゴム尋で形
成したパッジベージ茜ン膜、(至)は従来技術の特徴的
な半田等の金属配線である。
In the figure, (1) is an N high resistivity semiconductor substrate, (2) is a p
A high resistivity semiconductor substrate, each of which has a first conductivity type opposite to the lamp.
.. There are second gate regions +3+ and +41, which control on/off of the main current flowing between the cathode +N low resistance region (5) and the anode P low resistance region (6). +7) 18
+ +9) tl (D is the cathode, anode, the first
The gate, the electrode wiring of the second gate part, antiz are the high resistivity channel bright areas that serve as the path for the main current flowing between the anode (6) and the power sword (5), (13 is the mechanical reinforcement of the element and the load sink) 111 L of the second gate electrode wiring αG, and the gate part Mai in the center of the part
ll (14 is insulated with an insulating ceramic seal α9, and the Mo part around the element is also insulated with an insulating ceramic seal U■. 07) is a mechanical-electrical seal around the element where the PN junction is glH. The padding film is made of St rubber for stability, and is a metal wiring such as solder, which is characteristic of the prior art.

次に動作について説明する。Next, the operation will be explained.

DG−8I Thは第1ゲート(3)−力ソード(5)
間及び第2ゲート(4)−丁ノード(6)間に印加する
順または逆バイアスによって、主電流通路となるチャネ
ル領域Qll(121部で空乏層を消滅生成させ、チャ
ネル領域(Ill(2)を開閉させる事によって主電流
を0N−OFFする。従って、主電流通路を限られた素
子面積内でIB来る限り沢山取りかつ、ゲート逆バイア
ス時の逆バイアス電圧を出来るだけ高く出来る様にする
為には、第1ゲートとカソード或は第2ゲートとアノー
ドが3次元的な配直になる埋込みゲート構造が有効であ
る。この構造の場合、ゲートを取り出す為にはカソード
及びアノード部をメサエッチで島状に残した形になるの
で、ゲート部分の電極取り出し部とアノード及びカソー
ド電極部で約30μmlの段差が生じる。
DG-8I Th is 1st gate (3) - Power sword (5)
By applying a forward or reverse bias between the gate and the second gate (4) and the node (6), a depletion layer is generated in the channel region Qll (121), which becomes the main current path, and the channel region (Ill (2) By opening and closing, the main current is turned 0N-OFF.Therefore, in order to take as many main current paths as possible within the limited element area and to make the reverse bias voltage as high as possible when the gate is reverse biased. A buried gate structure in which the first gate and cathode or the second gate and anode are arranged three-dimensionally is effective.In this structure, in order to take out the gate, the cathode and anode parts must be mesa-etched. Since it is left in the form of an island, a step difference of about 30 μml is created between the electrode extraction portion of the gate portion and the anode and cathode electrode portions.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来のDG−9IThの様な大谷針バイポーラ型半導体
スイッチング装置は以上の様に構成されていたので下記
の様な問題点があった。
Since the conventional Otani needle bipolar semiconductor switching device such as DG-9ITh was constructed as described above, it had the following problems.

第1に、素子中央ゲート取り1136部が前述の様に数
10μ風くぼんだ形になっている為に、本来は陽極MO
円板の中央ゲート電極取14)部を素子側のくぼみ具合
に応じて突lHt、た形状にしておく事が望ましいが、
Mo板表面粗さの加工精度、絶縁セラミックシールの構
造、素子側段差のばらつき専を考慮すれば、事実上不可
能であるため、第4図に示した様に素子側或はMO側Q
4)の少(とら一方に中日電極(財)の様な段差形状に
対しである程度加熱融解や変形などによって融通性か生
じる電極材料を用いて配線を行わなくてはならないので
、電極形状の制御性が悪く、素子の信頼性が取れにくい
と云う問題があった。
First, since the central gate portion 1136 of the element is recessed in the shape of several tens of micrometers as mentioned above, it was originally the anode MO.
It is desirable that the center gate electrode recess 14) of the disk be shaped into a convex shape depending on the degree of depression on the element side.
Considering the machining accuracy of the Mo plate surface roughness, the structure of the insulating ceramic seal, and the variations in the level difference on the element side, it is virtually impossible to
4) On one side, wiring must be done using an electrode material that is flexible due to heating, melting, deformation, etc. for a stepped shape like the one made by Chunichi Electrode Co., Ltd.; There were problems in that controllability was poor and device reliability was difficult to obtain.

第2に、本来、サイリスタ等の大電力素子は隅板Mo電
極等との電気的・機械的・熱的密着性を良くするために
、 A/金合金法で半導体基板と陽極板とを貼り付ける
のであるが、ゲート電極取りIn L部分が第4図00
の様にくぼんでいるので、ゲート部分の合金接着か不可
能で、従ってこの場合も、素子電気特性の長期に渡る信
頼性確保が煤かしいと云う問題があった。
Second, in order to improve the electrical, mechanical, and thermal adhesion of high-power devices such as thyristors with corner plate Mo electrodes, etc., the semiconductor substrate and anode plate were originally attached using the A/gold alloy method. However, the gate electrode In L part is shown in Fig. 400.
Since the gate is recessed, it is impossible to bond the alloy to the gate portion, and therefore, in this case as well, there is a problem in that it is difficult to ensure the long-term reliability of the device's electrical characteristics.

第3に、素子のパッケージ組立ての際に、数100Kf
f/cdの圧力で素子圧接を行うが、中央第2ゲート部
が広範囲にわたり陽極板Mo板と離れた状態であるので
、圧接圧力をあまり大きくとれず、lk極側のカソード
電極配線や第1ゲートの電極配線部での接触抵抗が不安
定になるε云う問題があった。
Thirdly, when assembling the device package, several hundred Kf
The elements are pressure-welded at a pressure of f/cd, but since the central second gate part is separated from the anode plate Mo plate over a wide area, it is not possible to maintain a very large pressure-welding pressure, and the cathode electrode wiring on the lk electrode side and the first There was a problem of ε, which made the contact resistance at the electrode wiring part of the gate unstable.

第4に、半導体基板と陽極板の少くとも一方に数10μ
汎の厚膜金属電極を設ける工程が必要なために、工程的
にもA/金合金法よる接着工程より複雑かつ長くなると
云う問題があった。
Fourthly, at least one of the semiconductor substrate and the anode plate has a thickness of several tens of μm.
Since the process of providing a general-purpose thick film metal electrode is required, there is a problem that the process is more complicated and longer than the bonding process using the A/gold alloy method.

この発明は上記の様な問題点を解消する為になされたも
ので、埋込みゲート電極の取り出しを容易にすると同時
に、電気的1機械的な長期信頼性の高い大容緻バdポー
ラ型半導体スイッチング装置を精度良く間車な工程で得
る事を目的とする。
This invention was made to solve the above-mentioned problems, and at the same time facilitates the removal of the buried gate electrode, it also provides a large-capacity, high-density, bad d-polar type semiconductor switching device with high long-term electrical and mechanical reliability. The purpose is to obtain a device with high precision and a slow process.

〔課題を解決するための手段〕 この発明に係るバイポーラ型半導体スイッチング装置は
、埋込みゲートの取りIB L部を陰極又は陽極の少く
とも一方と同じ高さで電極を取りIBす様にしたもので
ある。
[Means for Solving the Problems] A bipolar semiconductor switching device according to the present invention is such that the IBL portion of the buried gate has an electrode at the same height as at least one of the cathode and the anode. be.

〔作用〕[Effect]

この発明における埋込みゲート電極の一部を又ッチング
により堀り出す事をせずに、陰極又は陽極と同じ高8の
まま残し、場合によっては表面に埋込みゲート領域と同
一の導伝型領域を形成する事により、ゲート部分の電極
取りIBシを容易にし、素子の電気的5機械的信頼性を
向上させる。
In this invention, a part of the buried gate electrode is not excavated by etching, but is left with the same height of 8 as the cathode or anode, and in some cases, a region of the same conductivity type as the buried gate region is formed on the surface. By doing so, electrode removal at the gate portion is facilitated and the electrical and mechanical reliability of the device is improved.

〔実施例〕〔Example〕

以下、この発明の一実施例を図について説明する。第1
図において、前記従来のらのと異なる部分は、0校の第
2ゲート取りIHt、用突起部と、この部分を全体に覆
う(11の第2ゲート取り出用電極配線である。他の符
号は前記従来のものと同一にっき説明は省略する。
An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, the parts that are different from the conventional one are the protrusion for the second gate IHt of 0, and the electrode wiring for the second gate 11 that completely covers this part.Other symbols is the same as the conventional one, so the explanation will be omitted.

次に動作について説明する。Next, the operation will be explained.

この実施例では中央第2ゲート面上の一部をエツチング
等により堀り出さずに残した形になっているので、ゲー
トの表面は他の陽極部電極(8)と同一の烏さになり、
この部分の第2ゲート取り1)3シ用電極配線Q’lを
、アノード電極配線(8)と同一工程で同一材料、同一
厚みで同時に形成する。従って陽極板α諌とアノード電
極配線(8)の接合と同程度の接触抵抗、機械強度及び
電気的信頼性で、第2ゲート取り1hシ用電極配線tl
lと陽極板中央ゲート部Mo!1t14を接続する事が
出来、パッケージの際の大きな圧接圧力にも耐え得る機
械的強度を素子に持たせる事が1b来る。
In this example, a part of the central second gate surface is left unexcavated by etching, etc., so the surface of the gate has the same shape as the other anode electrode (8). ,
The second gate of this part is formed at the same time as the anode electrode wiring (8) using the same material and thickness in the same process as the anode electrode wiring (8). Therefore, the contact resistance, mechanical strength, and electrical reliability are the same as those of the connection between the anode plate α and the anode electrode wiring (8), and the electrode wiring tl for the second gate opening 1h
l and anode plate central gate part Mo! It is possible to connect 1t14, and it is possible to provide the element with mechanical strength that can withstand large pressure during packaging.

なお、上記実施例では中央第2ゲート直上の部分をエツ
チングせずに残しただけの表面に、堀1bした第2ゲー
ト表面まで延在きせる形で第2ゲート取りtBシ用電極
配線a湯を形成した形であるが、第2図に示す実施例で
は、中央第2ゲート取り出し用突起部(1g+の表面を
第2ゲートと同一の導EJI(この場合は、N型領域)
領域■を形成し、モの表面の一部に第2ゲート取りIB
 t、用電極配線Qqを形成して屯、同様の効果を得る
事か#B来る。
In addition, in the above embodiment, the electrode wiring a for the second gate is placed on the surface of the portion directly above the second gate in the center that is left without being etched, in such a way that it extends to the surface of the second gate where the trench 1b is formed. However, in the embodiment shown in FIG.
Form a region ■, and form a second gate IB on a part of the surface of the
It is possible to obtain the same effect by forming electrode wiring Qq for #B.

又、第2図の実施例では第2ゲート取りIB L円電極
配線a9を陽極Mo板α諌の中央第2ゲート取り出し用
ゲート部Mo棒圓と接する部分だけに形成する構造εし
た場合を示したが、この中央第2ゲート取りIB t、
用電極配線曲を、第1図の様に埋込みゲート堀IM L
、部表面まで延在させても良い。
Further, the embodiment shown in FIG. 2 shows a structure ε in which the second gate IBL circular electrode wiring a9 is formed only in the part of the anode Mo plate α in contact with the central second gate extraction gate portion Mo rod round. However, this central second gate IB t,
The electrode wiring curve for the buried gate trench IM L as shown in Figure 1.
, may extend to the surface of the part.

第1図、第2図の実施例では、埋込みゲート取りIBL
、のメサ型突起部分をアノード側一方だけに形成した場
合について説明したが、第3図の様に埋込みゲート取り
IHL突起部をアノード側・カソード側の両方に形成す
る事もtb来る。この場合は、カソード側ゲート取り出
しがカソード部と同一平面に形成されるので、単導体素
子を陽極板等に貼り付けず機械的な圧接だけによるパフ
ケージングを行うフルプレス方式に適合しやすくなる。
In the embodiments shown in FIGS. 1 and 2, the buried gate IBL
Although the case has been described in which the mesa-shaped projection portion of , is formed only on one side of the anode side, it is also possible to form the buried gate IHL projection portion on both the anode side and the cathode side as shown in FIG. In this case, since the cathode side gate extraction is formed on the same plane as the cathode part, it becomes easily applicable to the full press method in which the single conductor element is not attached to the anode plate or the like and puff caging is performed only by mechanical pressure bonding.

又、上記実施例では、埋込ゲート型のDG−8IThに
ついて説明したが、GTO(Gate−工uru−OF
F)サイリスタを初め、バイポーラ型半導体スイッチン
グ素子全体に適用する事がlo来る。
In addition, in the above embodiment, the buried gate type DG-8ITh was explained, but the GTO (Gate-Full-OF)
F) It will soon be possible to apply it to all bipolar semiconductor switching elements, including thyristors.

〔発明の効果〕〔Effect of the invention〕

以上の様VC,!−の発明によれば、埋込みゲートの取
り出し電極の一部をカソードとアノードの少なくとも一
方と同一高さの平面から取り♂bす様に構成したので、
各電極部接触抵抗が小さく安定した、又、A/金合金法
が適用!お来る等素子全体の電気的機械的特性の安定し
た信頼性の高いものが得られる効果がある。
That's all VC,! According to the invention of -, a part of the lead-out electrode of the buried gate is taken out from a plane at the same height as at least one of the cathode and the anode.
The contact resistance of each electrode part is small and stable, and the A/gold alloy method is applied! This has the effect of providing stable and highly reliable electromechanical properties of the entire device.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例による大容置バイポーラ型
半導体スイッチング装置の例である両面埋込みゲート型
静電誘導サイリスタを示す断面模式図、第2図及び第3
図はこの発明の他の実施例を示す第1図と同種の半導体
スイッチング装置の断面模式図、第4図は従来技術の半
導体スイッチング装置の断面模式図である。 図において、+11 、 (21は各々N型、P型窩比
抵抗半導体基板、 +3114+は各々第1ゲートP型
、第2ゲー)−N型低抵抗餉域、+51 (6)は各々
カソードN型、アノードP型低抵抗領域、17) +8
1は各々カソード、アノード電極配線、(9) 1it
)は各々第1.第2ゲート電極配線、(11) tlZ
は各々カソード側・アノード測高比抵抗チャネル領域、
03はアノードMo板、(141はゲート部Mo棒、i
19はアノード−第2ゲート間絶縁用セラミックシール
、00は絶縁用セラミックシール、0のはパフシベーシ
タン膜、 os G!第2ゲート取りlおし用突起部、
 (1!Jは第2ゲート取り/BL、用電極配線。 ■は第2ゲーF取り出し用突起部表面の第2ゲート乏同
−導伝型明域、Qυは、第1ゲート取りIB L用突起
部、■は第1ゲート取り出し用突起部表面の第1ゲート
と向−導伝型舶載、■は第1ゲート取り/HL、用電極
配線を示す。 向、図中、同一符号は同一、又は相当部分を示す。
FIG. 1 is a schematic cross-sectional view showing a double-sided buried gate type electrostatic induction thyristor which is an example of a large-capacity bipolar semiconductor switching device according to an embodiment of the present invention, and FIGS.
The figure is a schematic sectional view of a semiconductor switching device of the same type as FIG. 1 showing another embodiment of the present invention, and FIG. 4 is a schematic sectional view of a semiconductor switching device of the prior art. In the figure, +11, (21 are N type and P type hole resistivity semiconductor substrates respectively, +3114+ are first gate P type and second gate respectively) -N type low resistance hook region, +51 (6) are each cathode N type , anode P-type low resistance region, 17) +8
1 is each cathode and anode electrode wiring, (9) 1it
) are the first. Second gate electrode wiring, (11) tlZ
are the cathode side and anode height measurement resistivity channel regions, respectively,
03 is an anode Mo plate, (141 is a gate Mo rod, i
19 is an insulating ceramic seal between the anode and the second gate, 00 is an insulating ceramic seal, 0 is a puffy basitan film, os G! 2nd gate recess l protrusion,
(1!J is the electrode wiring for the second gate/BL, ■ is the second gate poor conduction type bright area on the surface of the projection for taking out the second gate F, Qυ is the first gate IBL, The protrusion, ■ indicates the first gate on the surface of the protrusion for taking out the first gate, and the electrode wiring for the conductive type ship, and ■ indicates the electrode wiring for the first gate/HL. , or a corresponding portion.

Claims (1)

【特許請求の範囲】[Claims] 第1及び第2主電極が主電流通路となる半導体基板を挾
んで両主面に形成されており、少なくとも一方の主電極
の近傍の半導体基板中に主電流のオン・オフを制御する
埋込みゲート電極領域を有するバイポーラ型半導体スイ
ッチング装置において、この埋込みゲートの取り出し部
をメサ形状で形成した少なくとも一方の主電極とほぼ同
一平面上に形成した事を特徴とするバイポーラ型半導体
スイッチング装置。
First and second main electrodes are formed on both main surfaces sandwiching a semiconductor substrate serving as a main current path, and a buried gate is formed in the semiconductor substrate near at least one of the main electrodes to control on/off of the main current. 1. A bipolar semiconductor switching device having an electrode region, characterized in that a lead-out portion of the buried gate is formed substantially on the same plane as at least one main electrode formed in a mesa shape.
JP21963289A 1989-08-24 1989-08-24 Bipolar type semiconductor switching device Pending JPH0382080A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21963289A JPH0382080A (en) 1989-08-24 1989-08-24 Bipolar type semiconductor switching device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21963289A JPH0382080A (en) 1989-08-24 1989-08-24 Bipolar type semiconductor switching device

Publications (1)

Publication Number Publication Date
JPH0382080A true JPH0382080A (en) 1991-04-08

Family

ID=16738571

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21963289A Pending JPH0382080A (en) 1989-08-24 1989-08-24 Bipolar type semiconductor switching device

Country Status (1)

Country Link
JP (1) JPH0382080A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008079959A (en) * 2006-09-28 2008-04-10 Tachikawa Blind Mfg Co Ltd Ring runner for decorative curtain rail

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56130969A (en) * 1980-03-18 1981-10-14 Hitachi Ltd Semiconductor device
JPS6031266U (en) * 1983-04-19 1985-03-02 吉武 一男 Relaxation prevention device for curtain opening/closing wires in greenhouses, etc.
JPS61182260A (en) * 1985-02-08 1986-08-14 Toshiba Corp Gate turn-off thyristor
JPS62234370A (en) * 1986-04-04 1987-10-14 Fuji Electric Co Ltd Gto thyristor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56130969A (en) * 1980-03-18 1981-10-14 Hitachi Ltd Semiconductor device
JPS6031266U (en) * 1983-04-19 1985-03-02 吉武 一男 Relaxation prevention device for curtain opening/closing wires in greenhouses, etc.
JPS61182260A (en) * 1985-02-08 1986-08-14 Toshiba Corp Gate turn-off thyristor
JPS62234370A (en) * 1986-04-04 1987-10-14 Fuji Electric Co Ltd Gto thyristor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008079959A (en) * 2006-09-28 2008-04-10 Tachikawa Blind Mfg Co Ltd Ring runner for decorative curtain rail

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