JPH0384645U - - Google Patents
Info
- Publication number
- JPH0384645U JPH0384645U JP14545189U JP14545189U JPH0384645U JP H0384645 U JPH0384645 U JP H0384645U JP 14545189 U JP14545189 U JP 14545189U JP 14545189 U JP14545189 U JP 14545189U JP H0384645 U JPH0384645 U JP H0384645U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- primary
- circuit section
- section
- pass filter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000003111 delayed effect Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 6
- 230000003321 amplification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
Landscapes
- Noise Elimination (AREA)
Description
第１図は本考案の原理構成を示すブロツク図、
第２図は本考案の第１実施例を示す回路図、第３
図は本考案の第２実施例を示す回路図、第４図は
第２図の変形例を示す回路図、第５図は従来の雑
音除去装置を示すブロツク図、第６図は第５図に
おける入力信号と出力信号との関係を示す図、第
７図は従来のＬＰＦおよび移相器の具体例を示す
回路図である。
図において、１……第１のＲＣ回路、２……第
２のＲＣ回路、３……ＬＰＦ、４……移相器、５
……切替回路、１０……１次ＲＣ回路部、１２…
…バツフアアンプ、１４……信号処理部、１５…
…演算処理部、２０……２次ＲＣ回路部、２４…
…増幅部器、２５……減算器。
Figure 1 is a block diagram showing the principle configuration of the present invention.
Figure 2 is a circuit diagram showing the first embodiment of the present invention;
Figure 4 is a circuit diagram showing a second embodiment of the present invention, Figure 4 is a circuit diagram showing a modification of Figure 2, Figure 5 is a block diagram showing a conventional noise removal device, and Figure 6 is Figure 5. FIG. 7 is a circuit diagram showing a specific example of a conventional LPF and a phase shifter. In the figure, 1...first RC circuit, 2...second RC circuit, 3...LPF, 4...phase shifter, 5
...Switching circuit, 10...Primary RC circuit section, 12...
...Buffer amplifier, 14...Signal processing section, 15...
...Arithmetic processing section, 20...Secondary RC circuit section, 24...
...Amplification unit, 25...Subtractor.
Claims (1)
信装置内の入力信号Ｓｉに混入する雑音を除去す
るローパスフイルタ３と、 少なくとも１段のＲＣ回路を含み、かつ、前記
ローパスフイルタによる前記入力信号Ｓｉの位相
遅れを補正する移相器４と、 前記雑音の有無に応じてそれぞれ前記ローパス
フイルタ３または前記移相器４を選択して出力信
号Ｓ０を生成する切替回路５とを有する雑音除去
装置において、 前記ローパスフイルタ３の前記ＲＣ回路の一部
と前記移相器４の前記ＲＣ回路とを共用すること
を特徴とする雑音除去装置。 ２ 前記ローパスフイルタ３が、１段の前記ＲＣ
回路からなる１次ＲＣ回路部１０と、該１次ＲＣ
回路部１０にバツフアアンプ１２を介して接続さ
れる１段の２次ＲＣ回路部２０とを有し、 前記移相器４が、前記１次ＲＣ回路部１０と、
該１次ＲＣ回路部１０からの遅延信号Ｓｅならび
に前記入力信号Ｓｉを演算処理して前記位相遅れ
を補正するための演算処理部１５とを有する請求
項１記載の雑音除去装置。 ３ 前記ローパスフイルタ３が、１段の前記ＲＣ
回路からなる１次ＲＣ回路部１０と、該１次ＲＣ
回路部１０にバツフアアンプ１２を介して接続さ
れる１段の２次ＲＣ回路部２０とを有し、 前記移相器４が、前記１次ＲＣ回路部１０と、
該１次ＲＣ回路部１０からの前記遅延信号Ｓｅを
所定の利得だけ増幅する増幅部２４と、該増幅部
２４の出力から前記入力信号Ｓｉを減算して前記
位相遅れを補正するための減算器２５とを有する
請求項１記載の雑音除去装置。[Claims for Utility Model Registration] 1. A low-pass filter 3 that includes at least two stages of RC circuits and removes noise mixed in the input signal Si in the receiving device; and at least one stage of RC circuits; a phase shifter 4 that corrects a phase delay of the input signal Si caused by the low-pass filter; and a switch that selects the low-pass filter 3 or the phase shifter 4 depending on the presence or absence of the noise to generate the output signal S0 . circuit 5, wherein a part of the RC circuit of the low-pass filter 3 and the RC circuit of the phase shifter 4 are shared. 2 The low-pass filter 3 has one stage of the RC
A primary RC circuit section 10 consisting of a circuit, and the primary RC
A one-stage secondary RC circuit section 20 is connected to the circuit section 10 via a buffer amplifier 12, and the phase shifter 4 is connected to the primary RC circuit section 10,
2. The noise removal device according to claim 1, further comprising an arithmetic processing section 15 for arithmetic processing the delayed signal Se from the primary RC circuit section 10 and the input signal Si to correct the phase delay. 3 The low-pass filter 3 has one stage of the RC
A primary RC circuit section 10 consisting of a circuit, and the primary RC
A one-stage secondary RC circuit section 20 is connected to the circuit section 10 via a buffer amplifier 12, and the phase shifter 4 is connected to the primary RC circuit section 10,
an amplifier section 24 that amplifies the delayed signal Se from the primary RC circuit section 10 by a predetermined gain; and a subtracter that subtracts the input signal Si from the output of the amplifier section 24 to correct the phase delay. 2. The noise removal device according to claim 1, comprising: 25.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14545189U JPH057786Y2 (en) | 1989-12-19 | 1989-12-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14545189U JPH057786Y2 (en) | 1989-12-19 | 1989-12-19 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0384645U true JPH0384645U (en) | 1991-08-28 |
| JPH057786Y2 JPH057786Y2 (en) | 1993-02-26 |
Family
ID=31692086
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14545189U Expired - Lifetime JPH057786Y2 (en) | 1989-12-19 | 1989-12-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH057786Y2 (en) |
-
1989
- 1989-12-19 JP JP14545189U patent/JPH057786Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH057786Y2 (en) | 1993-02-26 |
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