JPH0388024A - Arithmetic unit for vector floating point - Google Patents

Abstract

PURPOSE:To shorten operation time by the time to be required for shifting a mantissa part by constituting the arithmetic unit so as to immediately executing addition/subtraction without shifting the mantissa part when the exponential parts of arithmetic data are equal as the result of comparison. CONSTITUTION:A selection circuit 6 selects the mantissa part of output data outputted from an operation start time register 1 and then selects output data outputted from a shifted result register 36 in a shift circuit 3 after '1' from the start of the operation. A selection circuit 7 selects the mantissa part of output data of a register 2 and the output data of a shifted result register 37. A selection circuit 8 similarly selects the exponential part of the output data of the register 1 and the output data of an exponential part selection circuit result register 35. Since these selection circuits 6 - 8 are provided, an operation result to be obtain in the case of having the same exponential part is outputted after '21' from the start of the operation and an operation result having unequal exponential parts is outputted after '31'.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a vector floating point arithmetic unit, and more particularly to speeding up iteration operations in a vector arithmetic processing unit.

Prior Art Conventionally, this type of vector floating point addition/subtraction device has a third
As shown in the figure, a first operand register 1 and a second operand register 2 are used to hold floating point data.
And regarding the data output from each register 1.2,
A shift circuit 3 that shifts the mantissa data with the smaller exponent part to the right depending on the magnitude of the exponent part of the data, an arithmetic circuit 4 that receives the mantissa output data of the shift circuit 3, and the arithmetic result of the arithmetic circuit 4. and a normalization circuit 5 which manually normalizes the exponent part output data of the shift circuit 3 so that the bit representation of the mantissa part is maximized.

Register 1 is a register that holds either the data output from a data holding device such as a vector register (not shown) or the calculation result output by the normalization circuit 5, and register 2 is a data holding device such as a vector register (not shown). This is a register that holds data output from.

The shift circuit 3 is a circuit for matching the exponent parts of floating point data to which addition and subtraction are performed by shifting the smaller mantissa data of the exponent part data to the right, and has a configuration as shown in FIG.

The shift circuit 3 calculates the exponent part from the comparison result of the exponent part comparison circuit 31 which calculates the difference value between the exponent part data and the difference value between the exponent part data of the output data of the register 1.2. The exponent selection circuit 32 selects the larger exponent data, and the comparator circuit 31 selects the smaller exponent data based on the comparison result output from the comparator 31 for the mantissa data in register 1.2 and the difference value between the exponent parts. A first operand shift circuit 33 and a second operand shift circuit 34 that shift the mantissa part of the operand to the right, a register 35 that holds the output data of the exponent part selection circuit 32, and a register that holds the output data of the ml operand shift circuit 33. 36 and a register 37 that holds the output data of the second operand shift circuit 34, tl! I have been.

The arithmetic circuit 4 is composed of a circuit that receives each mantissa data output from the shift circuit 3 and performs addition and subtraction of absolute values, and a register that holds the arithmetic results.

As shown in FIG. 5, the normalization circuit 5 includes a normalization amount calculation circuit 51 that detects consecutive °0's from the most significant bit position of the mantissa calculation result and outputs a count value of the '0's. , an exponent part determination circuit 52 that subtracts the count value output from the normalization amount calculation circuit 51 from the exponent part data output from the shift circuit 3 to obtain an exponent part subtraction result; and a mantissa output from the arithmetic circuit 4. The shift circuit 53 performs a left shift on the partial data by the number of bits corresponding to the count value of the normalized ffi calculation circuit 51.

It is suitable for such a vector floating point adder/subtractor, V
O(i)-VO(i-1))Vl (i)i-1,2
, . . . , N will be described below.

When i-2, registers 1 and 2 contain V output from a data device such as a vector register.

(1) and V l (2) are set, and the shift circuit 3,
A calculation result is obtained via the calculation circuit 4 and the normalization circuit 5.

When i-3, 4, ..., N, register 1 is set to the l-1st operation result, and register 2 is set to the data of Vl (i) as in the case of i-2. An operation is performed. Therefore, when the processing time of the shift circuit 3, the arithmetic circuit 4, and the normalization circuit 5 is g during the iteration operation, the arithmetic operation is as shown in FIG.

In this way, during the iteration calculation, the i+1th calculation is not started until the i-th calculation is completed, so the calculation start timing is at 31 intervals.

Next, the operation of the shift circuit 3 will be explained.

For example, the exponent part of the data of the first operand is S,
Assume that the exponent part of the data of the ff12 operand is T, the difference value of the exponent part is U, and the magnitude relationship of the exponent part is S.
Assume that there is an AT relationship.

The exponent part comparison circuit 31 outputs a comparison result signal indicating SAT and the difference value U of the exponent part, and the selection circuit 32 outputs the exponent part S. Furthermore, since the exponent part of the first operand is larger, the shift circuit 33 has a shift amount of 0, and outputs the mantissa part data of the output data of the register 1 as is. The shift circuit 34 has registers 2 corresponding to the number of bits for the difference value U.
Shift the mantissa data of the output data to the right and output it.

If the magnitude relationship of the exponent part is T>S, the selection circuit 3
2 outputs the exponent part T, and the shift circuit 33 right-shifts the mantissa part data of the output data of the register 1 by the number of bits for the difference value U and outputs it.

The shift circuit 34 outputs the mantissa data of the output data of the register 2 as is.

In the shift circuit 3 that operates in this manner, if the exponent parts of each operand are equal, the selection circuit 32 selects either the exponent data of register 1 or the exponent data of register 2; Since the selection results are the same exponent part and the difference value is 0, the shift result of the shift circuit 33 is the same as the mantissa part data of register 1, and the shift result of the shift circuit 34 is also the same as the mantissa part data of register 2.
If the exponents are equal, the mantissa data of the first and second operands output by the shift circuit 3 and the selected exponent data are the mantissa data and exponent output from registers 1 and 2. The results are the same as the partial data.

In the conventional vector floating point addition/subtraction device described above, as described in the prior art, the mantissa output data of the shift circuit 3 is input to the arithmetic circuit 4, and the exponent output data of the shift circuit 3 is input to the normalization circuit 5. Therefore, floating point addition and subtraction with matching exponent parts that do not need to go through the shift circuit 3 have the drawback that the calculation time is long.

Purpose of the Invention Therefore, the present invention was made to eliminate such drawbacks of the conventional RANO, and its purpose is to reduce the calculation time when the exponent parts of both operands are the same. An object of the present invention is to provide a short vector floating point arithmetic unit.

Structure of the Invention According to the present invention, first and second floating-point data
exponent comparison means for comparing the exponent parts of the operands; and shifting means for shifting the mantissa part of the operand with the smaller exponent part according to the result of this comparison according to the difference in the exponent parts;
The vector floating point arithmetic device includes a calculation means for manually calculating the shift output and the mantissa of the operand having the larger exponent part, wherein the exponent parts are determined to be equal by the exponent part comparison means. Sometimes, the first and second
There is obtained a vector floating point arithmetic device characterized in that it has a control means for controlling the mantissa part of the operand of to be directly supplied to the arithmetic means.

Embodiment Next, a vector floating point arithmetic device according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. The vector floating point arithmetic device of the present invention includes a register 1 that holds either first operand data or operation result data;
A register 2 that holds second operand data and an operation start timing determining circuit 9 that determines the start timing of an operation based on the comparison result of the exponent part output from the exponent part comparison circuit 31 (see FIG. 4) of the shift circuit 3. , a shift circuit 3 that shifts the smaller mantissa part of the exponent part of the output data of register 1 or 2 to the right by the number of bits corresponding to the difference value of the exponent part, and shifts the mantissa part data output from register 1. Shift result register 36 of circuit 3 (see Figure 4)
a selection circuit 6 for selecting mantissa data output from the
Mantissa data output from register 2 and shift circuit 3
a selection circuit 7 for selecting the mantissa data output from the shift result register 37 (see FIG. 4);
A selection circuit 8 selects the exponent data output from the exponent part data output from the exponent part data output from the exponent part selection result holding register 35 (see FIG. 4) of the shift circuit 3, and the mantissa output from the selection circuits 6 and 7. The bits of the mantissa are calculated from the exponent data output from the selection circuit 8 and the mantissa data output from the arithmetic circuit 4. It is constituted by a normalization circuit 5 that performs normalization so that the expression is maximized.

Next, the calculation start timing determining circuit 9 will be explained. For example, the calculation start timing determining circuit 9 calculates VO(i
)=VO(i-1)+VI(i),i-1,2,・
This is a circuit that determines the timing for starting the i+1th calculation after starting the i-th calculation in the iteration calculations such as . . . , N.

This circuit 9 connects the exponent part of the data of the first operand and the second
If the exponent parts of the operand data are the same, the first timing to start the i+1st operation is 2g after the start of the i-th operation and the end of the operation, and if the exponent parts are different, the first timing is This is a circuit for determining, from the comparison result of the first exponent part, one of the timings between i + and the second timing for starting the th calculation, 3g after the start of the calculation and the end of the calculation.

The calculation start timing signal output from the calculation start timing determining circuit 9 is also used as a signal to control the set timing of registers 1 and 2, thereby controlling the start timing of the next calculation data.

FIG. 752 is a diagram showing an example of the calculation start timing determining circuit 9. The circuit shown in FIG. 2 generates the first and second timing signals 1 described above in advance, and selects the first timing signal when the exponent parts are equal based on the result of comparing the exponent parts. It is comprised of a selection circuit 91 that selects the second timing signal when the timing signals are not equal.

Next, the first and second operand selection circuits 6 and 7 and the exponent selection circuit 8 will be explained.

The selection circuit 6 selects the mantissa part of the output data of the register 1 at the start of the calculation, and selects the output data of the shift result register 36 of the shift circuit 3 g after the start of the calculation. The selection circuit 7 similarly selects the mantissa part of the output data of the register 2 and the output data of the shift result register 37. Selection circuit 8
similarly selects the exponent part of the output data of register 1 and the output data of exponent part selection circuit result register 35.

In this way, by providing the selection circuits 6 to 8, the calculation result when the exponent parts are equal is output 2fI after the start of calculation, and the calculation result when the exponent parts are unequal is output after 3fI. It is.

Figure 6 1: Vo (i), Vl (L) (1
) shows the operation of each stage of the iteration operation when all exponent parts are equal. As shown in FIG. 6, in the vector floating point subtraction device of the present invention, by using the gap in the pipeline that occurs at the time of an iteration instruction, operations with equal exponent parts and operations with unequal exponent parts can be performed by l. Calculations are performed using shifted pipelines, and the data set timings of registers 1 and 2 output by the start timing determining circuit 9 are controlled based on the comparison results of the exponent parts of the two calculation results, as shown in the embodiment of FIG. It is configured to select based on a signal.

As described above, in the vector floating point addition/subtraction device of the present invention, when all exponent parts are equal, the calculation time can be n2g+1) compared to the conventional n31).

Effects of the Invention As described above, according to the present invention, when the comparison results of the exponent parts of the calculation data are equal, addition and subtraction processing is performed immediately without shifting the mantissa part, so the calculation time is reduced accordingly. This has the effect of shortening the time.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a diagram showing an example of an operation start timing determining circuit, Fig. 3 is a block diagram of a conventional vector floating point addition/subtraction device, and Fig. 4 is a diagram of a shift circuit. FIG. 5 is a diagram showing an example of a normalization circuit, FIG. 6 is a timing chart showing the operation of the embodiment of the present invention, and FIG. 7 is a timing chart showing the operation of conventional vector floating point addition/subtraction processing. The chart shown in FIG. 8 is a diagram showing an example of the operation of the calculation start timing determining circuit shown in FIG. Explanation of symbols of main parts 3...Shift circuit 4...Arithmetic circuit 5...Normalization circuit 6゜7゜8...Selection circuit 9... ...Calculation start timing determination circuit

Claims (1)

[Claims] (1) An exponent part comparing means for comparing the exponent parts of the first and second operands, which are floating point data, and based on the comparison result, the mantissa part of the operand with the smaller exponent part is adjusted according to the difference between the exponent parts. A vector floating point arithmetic device comprising a shift means for shifting the exponent part by the exponent part comparison means, and an arithmetic means for inputting the shift output and the mantissa part of the larger operand of the exponent part. 1. A vector floating point arithmetic device, comprising: control means for controlling the mantissa parts of the first and second operands to be directly supplied to the arithmetic means when it is determined that the first and second operands are equal.