JPH039028U - - Google Patents
Info
- Publication number
- JPH039028U JPH039028U JP6737489U JP6737489U JPH039028U JP H039028 U JPH039028 U JP H039028U JP 6737489 U JP6737489 U JP 6737489U JP 6737489 U JP6737489 U JP 6737489U JP H039028 U JPH039028 U JP H039028U
- Authority
- JP
- Japan
- Prior art keywords
- reset signal
- circuit
- input
- output device
- reset
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
- 230000005856 abnormality Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Description
第１図は本考案の一実施例を示すブロツク図、
第２図はＶＭＥバス方式のシステムブロツク図、
第３図は従来例を示すブロツク図、第４図は第３
図におけるＶＭＥバス方式のＩ／Ｏライト命令の
動作タイムチヤート、第５図は第３図における異
常時の動作タイムチヤート、第６図は第１図の遅
延回路１８の一実施例を示す回路図、第７図は第
１図の動作タイムチヤートである。
１０……ＣＰＵ部、１２……Ｉ／Ｏ部、１３…
…ＶＭＥバス、１４……命令デコーダ（リセツト
作成回路）、１５……タイミング回路、１８……
遅延回路、１９……リセツト回路、２０……イン
バータ、２１，２２……ＪＫフリツプフロツプ、
２３……ナンド回路。
FIG. 1 is a block diagram showing an embodiment of the present invention.
Figure 2 is a system block diagram of the VME bus system.
Fig. 3 is a block diagram showing a conventional example, and Fig. 4 is a block diagram showing a conventional example.
5 is an operation time chart of an I/O write command using the VME bus method in the figure, FIG. 5 is an operation time chart at the time of an abnormality in FIG. 3, and FIG. 6 is a circuit diagram showing an embodiment of the delay circuit 18 in FIG. 1. , FIG. 7 is an operation time chart of FIG. 1. 10...CPU section, 12...I/O section, 13...
...VME bus, 14...Instruction decoder (reset creation circuit), 15...Timing circuit, 18...
Delay circuit, 19...Reset circuit, 20...Inverter, 21, 22...JK flip-flop,
23... Nando circuit.
Claims (1)
により、前記入出力装置の内部回路を初期化する
リセツト信号を作成し送出するＶＭＥバス方式に
おける前記入出力装置内のリセツト回路において
、 前記書込み命令により、前記入出力装置の内部
回路を初期化するリセツト信号を作成し送出する
リセツト信号作成回路と、 前記書込み命令動作の正常終了応答信号が前記
入出力装置から前記中央処理装置に対して送出さ
れ、一連の書込み命令終了後にリセツト信号を送
出できるように前記リセツト信号作成回路のリセ
ツト信号出力を遅延させて出力するための遅延回
路とを備えたことを特徴とするＶＭＥバス方式用
リセツト回路。[Claims for Utility Model Registration] A reset circuit in the input/output device in a VME bus system that creates and sends a reset signal for initializing the internal circuit of the input/output device in response to a write command from a central processing unit to the input/output device. a reset signal generating circuit that generates and sends a reset signal for initializing an internal circuit of the input/output device according to the write command; and a reset signal generating circuit that generates and sends a reset signal for initializing an internal circuit of the input/output device, and a normal completion response signal of the write command operation is transmitted from the input/output device to the central processing unit. and a delay circuit for delaying and outputting the reset signal output of the reset signal generation circuit so that the reset signal can be sent out after a series of write commands are completed. reset circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6737489U JPH039028U (en) | 1989-06-12 | 1989-06-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6737489U JPH039028U (en) | 1989-06-12 | 1989-06-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH039028U true JPH039028U (en) | 1991-01-29 |
Family
ID=31600892
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6737489U Pending JPH039028U (en) | 1989-06-12 | 1989-06-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH039028U (en) |
-
1989
- 1989-06-12 JP JP6737489U patent/JPH039028U/ja active Pending
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