JPH0391397A - Color signal processing unit - Google Patents

Abstract

PURPOSE:To reduce circuit components, to improve the reliability and to reduce the cost by devising the unit such that 2 systems of video color signals are subject to point sequential processing and one vertical filter is used to limit the vertical frequency. CONSTITUTION:Color signals PB, PR are subjected to point sequential processing, a vertical filter 5 is used in common for both the signals and the line sequential processing and the line replacement processing are implemented by a simple circuit comprising 3 latch circuits 6-8 and three line memories 12-14. Thus, no exclusive vertical filter is required for each video color signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a color signal processing device that performs line sequentialization and line replacement of two systems of video color signals.

[Prior Art] FIGS. 6A and 6B show a video color signal PB (for example, a blue difference signal) and PR (for example, a red difference signal), respectively. PBI, PR2,..., PRI, PBR2,...
◆◆ are signals for one line each.

By performing line sequentialization and line swapping of these two systems of color signals PB and PR, a single signal as shown in FIG. 7 is obtained.
Conventionally, a processing device as shown in FIG. 8 has been used to obtain the systematic color signal SC.

In the figure, color signals PB and PR from input terminals 40B and 4OR are converted into digital signals by A/D converters 41B and 4'lR, respectively, and then supplied to vertical filters 42B and 42H. Vertical frequency band limiting is performed to prevent aliasing.

The band-limited color signals PB' and PR' output from the vertical filters 42B and 42R are sent to the line sequential circuit 4.
3.

The line sequential joint N43 is constructed as shown in FIG.

That is, the color signals PB' and PR' (Fig. 10A
and B) are respectively three-state buffers 44
The output signals of these buffers 44B and 44R are combined, and this combined signal is output as a line sequential signal SC'.

Buffers 44B and 44R are supplied with control signals CB and CR (shown in C and D in the figure), respectively. The buffers 44B and 44R output color signals PB' and PR' from the output side when the control signals CB and CR are at a low level "L", and are high impedance when the control signals CB and CR are at a high level "H". configured to be in the state.

Therefore, a line sequential signal SC' obtained by combining the output signals of buffers 44B and 44R is obtained as shown in FIG. 10E.

Returning to the example in FIG. 8, the line sequential signal SC' from the line sequential circuit 43 is supplied to the line switching circuit 45.

The line switching circuit 45 is configured as shown in FIG.

That is, line sequential signal SC' is supplied to three-state buffer 46 and delay circuits 47 and 48. The delay circuit 47 and the delay time of 4 days are each one horizontal period (I
H) and two horizontal periods (2H). Then, the output signals of the 3-state buffer 46 and the delay circuits #i 47 and 48 are combined, and this combined signal is output as the color signal SC.

The buffer 46 and delay circuits 47 and 48 receive control signals C1, C2 and C3 (12th diagram,
E and F) are supplied.

When the control signals CI, C2, and C3 are at low level rLJ, the buffer 46 and delay circuits 47 and 48 output color signals from the output side (see A in the same figure).

B and C) are output, and the control signal C1
, C2 and C3 are at high level rHJ, the circuit is configured to be in a high impedance state.

Therefore, the color signal SC obtained by combining the output signals of the buffer 46, the delay circuit 47, and the fourth day is obtained as shown in FIG. 12G.

Returning to the example in FIG. 8, one system of color signals SC from the line switching circuit 45 is supplied to the output terminal 49.

[Problem to be solved by the invention] In this way, in the example of FIG. 8, two problems as shown in FIG.
From the color signals PB and PR of the systems, it is possible to obtain one system of color signals SC which is line-sequentialized and line-switched as shown in FIG.

However, according to the example in FIG. 8, the color signals PB and PR
Since each of these requires dedicated vertical filters 42B and 42R, it is disadvantageous in terms of the number of parts, cost, reliability, etc.

Therefore, the present invention aims to eliminate the above-mentioned disadvantages.

[Means for Solving the Problems] The present invention includes first and second A/D converters that convert first and second video color signals into digital signals, respectively, and the first and second A/D converters. A switch circuit that alternately selects sampling data from the A/D converter, a vertical filter that limits the vertical frequency of the output signal of this switch circuit, and an output signal of this vertical filter is supplied;
and a latch circuit that performs separation and line sequential processing of the second video color signal, and the output signals of this latch circuit are respectively supplied to three line memories that perform line replacement processing, and the latch circuit and line memory are provided with timing signals. and a timing generator that supplies pulses.

[Operation] In the above-described configuration, the first and second color signals PB and PR are converted into so-called point-sequential signals by the switch circuit 3, and one vertical filter 5 is shared. therefore,
There is no need for dedicated vertical filters for the color signals PB and PR.

[Embodiment] An embodiment of the present invention will be described below with reference to FIG.

In the figure, a color signal P from input terminals IB and IR is shown.
B and PR are A/D converters 2B and 2R, respectively.
and converted into a digital signal.

By the way, in the example of FIG. 8 described above, the vertical filters 42B and 4 are dedicated to the color signals PB and PR, respectively.
2R is used, but in this example, since one vertical filter is shared by color signals PB and PR, A
The sampling frequency in A/D converters 2B and 2R is set to twice the sampling frequency in A/D converters 41B and 41R in the example of FIG.

2A and 2B show the sampling state in this example, and FIGS. 2C and 2D show the sampling state in the example in FIG. 8. In the figure, fh is the horizontal frequency, fs is the sampling frequency of the conventional example, and fs' is the sampling frequency of the present example, and fs' = 2fs. Further, 81 to B2n and R1 to R2n are sampling data.

Color signal PB from A/D converter 2B (illustrated in Figure 3A)
is supplied to the switch circuit 3. The color signal PR (shown in FIG. 2B) from the A/D converter 2R is supplied to a delay circuit 4 having a delay time of 1/fs'. The color signal PR (shown in C in the figure) delayed by the delay circuit 4 is supplied to the switch circuit 3.

Switch circuit 3 has a duty of 50% at frequency fs.
A switching signal C01 (shown in the same figure) is supplied. In this switch circuit 3, the switching signal C01 is at a high level "H".
'', the color signal PB is selected, and when the switching signal COI is at the low level rLJ, the color signal PR is selected.

Therefore, as shown in FIG.
So-called dot-sequential color signals CC that are alternately selected at a cycle of /fs' are output.

By delaying the color signal PR in the delay circuit 4 as described above, the sampled data of the color signals PB and PR in the color signal CC become coincident.

The color signal cc outputted from the switch circuit 3 is supplied to a vertical filter 5, and the vertical frequency band is limited in order to prevent aliasing distortion due to line sequentialization. Band-limited color signal CC' output from this vertical filter 5
(Illustrated in FIG. 3F) are latch circuits 6, 7 and 8.
is supplied to

Further, 15 is a switch circuit, and this switch circuit 1
5 has a clock C with a frequency fs and a duty of 50%.
Ka (shown in FIG. 4B) is supplied, and at the same time, a clock CKb (shown in FIG. 4C) obtained by inverting the phase of this clock CKa by an inverter 16 is supplied.

9- Also, 9 is a ROM, and this ROM9 has a counter 1.
A count output of 0 is provided as an address signal. The counter 10 is supplied with the horizontal synchronizing signal HD as a clock and sequentially counts up each line. When one vertical period ends, the counter 10 is supplied with a reset pulse RE from the ROM 9 and is reset, and the count is counted up again line by line. .

The switching signal CO2 (shown in FIG. 5A) output from the ROM 9 is supplied to the above-mentioned switch circuit N15. This switching signal CO2 has a high level rH on odd lines.
J, is a signal with a duty of 50% and a frequency fh/2 such that the even numbered line is at a low level "L".

In the switch circuit 15, the switching signal CO2 is at a high level "
When the clock CKa is selected and the switching signal C
When O2 is at low level rLJ, clock CKb is selected. The clock output from switch circuit 15 is supplied to latch circuits 6, 7 and 8 as a latch pulse, and a latch operation is performed at the rising edge of the clock.

IO- In this case, the color signals CC' supplied to the latch circuits 6, 7 and 8 are the color signals PB' and PR' (the color signals PB', PR' are the color signals PB, PR
This is a dot-sequential color signal CC' in which sampling data of (the vertical frequency of which is band-limited) is arranged alternately at a period of 1/fs' (see FIG. 3F).

Therefore, during the horizontal period of the odd line when the clock CKa is selected by the switch circuit 15, the latch circuits 6.7 and 8
Then, the sampling data of the color signal PB' is latched (
On the other hand, during the horizontal period of the even line when the clock CKb is selected by the switch circuit 15, the sampling data of the color signal PR' is latched in the latch circuits 6, 7 and 8 (as shown in the figure E). ). That is, as shown in FIG. 5B, the latch circuits 6.7 and 8 separate the color signals PB' and PR' and output line-sequential color signals.

Color signals output from latch circuits 6.7 and 8 are supplied to line memories 12.13 and 111-4, respectively. These line memories 12, 13 and 14 each have a ROM 9 corresponding to the line number.
The read control signal CR'1. C
R2 and CR3 (Figure 5F).

G and H) are supplied.

Further, the read control signals CR1, CR2, and CR3 output from the ROM 9 are supplied to the latch circuit 11, and the latch circuit 11 is supplied with the read control signals CR1, CR2, and CR3 output from the ROM 9.
A clock CKI with a horizontal period is supplied. From this latch circuit 11, read control signals CRI, CR
Write control signals CW1.2 and CR3 are each delayed by one horizontal period. CW2 and CW3 (FIG. 5C, D and E) are output, and these write control signals CW1. CW2 and CW3 are supplied to line memories 12.13 and 14, respectively.

In addition, line memories 12, 13 and 14 contain 1/f
A clock CK2 with a period of s is supplied.

Line memories 12, 13 and 14 receive write control signals CW1. It operates when CW2 and CW3 and read control signals CRI, CR2 and CR3 are at a low level "L", and enters a high impedance state when they are at a high level rHJ.

Writing is performed in line memories 12, 13 and 14 based on write control signals CWI, CW2 and CW3. Figure 5 I.

J and K are the memory contents of the line memories 12, 13 and 14, respectively, and are written in the horizontal periods indicated by "*". That is, during the horizontal period of line 1, the color signal FBI' of line 1 is stored in the line memory 12.
During the horizontal period of line 2, the color signal PR2' of line 2 is stored in the line memory 13, the color signal PB3' of line 3 is stored in the line memory 14 during the horizontal period of line 3, and the color signal PB3' of line 3 is stored in the line memory 12 during the horizontal period of line 4. color signal PR4'
However, in line 5, the color signal PB5' of line 5 is stored in the line memory 14, and the color signals PR6' and P are stored in the same way in each line thereafter.
B7', . . . are written.

Further, reading is performed from line memories 12, 13 and 14 based on read control signals CR1, CR2 and CR3. In the fifth diagram, M and N are the stored contents of the line memories 12, 13 and 14, respectively, and are read out in the horizontal period indicated by "*". That is, in the horizontal period of line 3, the color signal FBI' of line 1 is transmitted from the line memory I2, in the horizontal period of line 4, the color signal PB3' of line 3 is transmitted from the line memory 14, and in the horizontal period of line 5, the color signal FBI' of line 1 is transmitted from the line memory 14.
In the horizontal period of line 6, the color signal PR2' of line 2 is inputted from the line memory 12, and the color signal PR4' of line 4 is inputted from the line memory 12.
However, in the horizontal period of line 7, the color signal PB5' of line 5 is read out from the line memory 14, and the color signals PB7', PR6', . . . are similarly read out for each line thereafter.

Further, the output signals of the line memories 12 to 14 are combined. As shown in FIG. 5, this composite signal is obtained by converting two color signals PB' and PR' line-sequentially into 14-color signals, and one color signal S having lines interchanged.
C, and this color signal SC is supplied to the output terminal 17.

As described above, according to this example, the color signals PB and PR are dot-sequentialized and the vertical filter 5 is shared, and the line-sequentialization and line replacement processes are performed by the three latch circuits 6 to 6.
8. This is carried out using a simple circuit consisting of three line memories 12-14. Therefore, according to this example, compared to the conventional example, it is possible to reduce the size of the circuit, improve reliability, and reduce costs.

Note that the order of line replacement is not limited to the above-described embodiment, and the order of line replacement can be arbitrarily changed by changing each control signal shown in FIG. 5C.

Further, in the above embodiment, three latch circuits 6 to 8
However, the number of latch circuits may be one. In this case, the output signal of the vertical filter 5 is 1
The output signals of the latch circuits are supplied to the line memories 12 to 15-14.

[Effects of the Invention] As described above, according to the present invention, two systems of video color signals are converted to point sequential, and the vertical frequency is limited by one vertical filter. In other words, there is no need for a dedicated vertical filter for each video color signal as in the conventional example, and it is possible to reduce circuitry, improve reliability, and reduce costs.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIGS. 2 to 5 are diagrams for explaining its operation, and FIGS. 6 to 12 are diagrams for explaining a conventional example. IR, IB 2R, 2B 3, 15 6-8. 11 - Input terminal - A/D converter - Switch circuit - Delay circuit - Vertical filter - Latch circuit 16-9 - 10 - 12-14 - 16 - 17 ◆ ROM - Counter - Line memory ◆ Inverter - Output terminal

Claims (1)

[Claims] (1) First and second A/D converters that convert first and second video color signals into digital signals, respectively; and sampling data from the first and second A/D converters. A switch circuit that alternately selects a signal, a vertical filter that limits the vertical frequency of the output signal of this switch circuit, and an output signal of this vertical filter is supplied, and the first and second video color signals are separated and line-sequentialized. A latch circuit that performs processing, three line memories that are each supplied with an output signal of this latch circuit and that performs line replacement processing, and a timing generator that supplies timing pulses to the latch circuit and line memories. Characteristic color signal processing device.