JPH0392016A - Parity circuit - Google Patents

Abstract

PURPOSE:To attain stable parity check with simple circuit constitution by providing a synchronizing type binary counter. CONSTITUTION:A synchronizing type binary counter 31 applies binary count in the timing of the rise of a timing clock signal 36 only when an input signal 34 inputted to a count enable terminal ENL is logic '1' and a binary count signal 41 is outputted from an output terminal QA. Then a logic '1' level of the binary count signal 41 is caught at a leading edge of a deciding position pulse 39 inputted to a clock terminal CLK of a D flip-flop 32 and outputted from an output terminal Q as a decision signal 42. Thus, a sampling circuit is eliminated and the circuit constitution is simplified, malfunction is less and the reliability is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a parity circuit, and particularly to a parity circuit that performs a parity check on a serial signal.

[Conventional technology]

Parity checking is widely used as an error detection method for data communication. In this method, a parity bit is added in advance so that the number of 1's or 0's contained in a group of data pits to be transmitted is an even or odd number, and the receiving side counts the number to check for errors. Therefore, on the receiving side, a means is required to count the number of "l" or "0" and determine whether it is an even number or an odd number.

Conventionally, the following parity circuit has been used as a means to achieve this.

The third rgJ represents this conventional parity circuit.

This circuit is equipped with a sampling circuit 11 having a human power terminal D1, a clock terminal CLK, and an output terminal Q. This output terminal Q is connected to the clock terminal CLK of the pinary counter 12, and this output terminal Q is connected to the clock terminal CLK of the pinary counter 12.
The output terminal QA of No. 2 is connected to the input terminal D of the D-type prep-prop l3. A determination position pulse signal 21 that designates a parity determination position, that is, a time point for determining even or odd numbers, is input to the clock terminal CLK of this D-type flip-flop l3.

FIG. 4 shows the operation when a signal such as the following equation (1) is input to this conventional parity circuit. However, in order to simplify the explanation here, human signal 1
It is assumed that the phase relationship between the timing clock signal 17 and the timing clock signal 17 has been properly adjusted in advance.

1011010... (1> The operation of the conventional parity circuit having the above structure will be explained with reference to FIG. 4.

The human power signal 15 (FIG. 4a) is input from the human power terminal 14 to the input terminal D of the sampling circuit l1.
It is sampled at the rising timing of the timing clock signal 17 (b in the same figure) applied from the clock input terminal l6 to the clock terminal CLK, and the signal is output from the output terminal D.
is output as a sampling signal 18 (C in the same figure). This sampling signal 18 is sent to the pinary counter 12.
When input to clock terminal CLK of D, binary count signal 19 (d in the figure) is output from output terminal QA, and D
It is supplied to the input terminal D of the type flip-flop 13. When the judgment position pulse signal 2l having the timing shown in FIG.
(f in the figure) is output from the output terminal Q via the external output terminal 23.

If it is predetermined in advance that when this judgment signal 22 is a logic "1", the number of bits "1" is an odd number, and when it is a logic "0", the number of bits "1" is an even number, then in this example, the judgment signal is a logic "1". Therefore, it is determined that the number of bits "1" is an odd number.

[Problem to be solved by the invention]

In such a conventional parity circuit, as mentioned above,
It is necessary to adjust the input signal 15 and the timing clock signal 16 in advance so that they have an appropriate phase relationship before sampling. This is because if sampling is simply performed using a logic gate, noise will occur at the changing points of the input signal l5 and the timing clock signal 17, causing the pinary counter 12 in the subsequent stage to malfunction, making it impossible to perform a normal parity judgment. Because it will disappear. Therefore, as a measure to prevent this, input conditions,
It is necessary to construct a parity circuit using a sampling circuit that takes into account operating element standards and temperature and environmental changes. For this reason, conventional parity circuits have disadvantages in that the circuit scale becomes large and the time required for designing and manufacturing increases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a parity circuit that can perform a stable parity check with a simple circuit configuration.

[Means to solve the problem]

In the present invention, (i) 200 million counting means that performs binary counting in synchronization with a clock signal of a predetermined cycle only when the input binary signal has a predetermined logical value;
(ii> Corresponding signal output means for outputting a signal corresponding to an even number or an odd number of bits having a predetermined logical value input up to a certain point based on the count value output from the binary counting means; is provided in the parity circuit.

In the present invention, it is determined whether the number of bits of the predetermined logical value up to that point is even or odd, based on the logical value of the signal corresponding to even and odd numbers output from the corresponding signal output means.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to Examples.

FIG. 1 shows a parity circuit in one embodiment of the present invention.

This circuit is equipped with a synchronous pinary counter 31 having a count enable terminal ENL, a clock terminal CLK, and an output terminal QA, and the output terminal QA is connected to a human power terminal D of a D-type flip-flop 32. A human input signal 34 is input to the count enable terminal ENL from an input terminal 33, and a timing clock signal 36 of a predetermined period is input from a clock input terminal 35 to the clock terminal CLK.

In addition to the input terminal D, the D-type flip-flop 32 has a clock terminal CLK and two output terminals QS (:i
Of these, the clock terminal CLK is connected to the determination position pulse input terminal 38, and the output terminal Q is connected to the external output terminal 37.

The operation of the parity circuit having the above structure will be explained with reference to FIG.

As an example, a human signal 3 such as the equation (1) reproduced below
4 will be explained.

“1011010...” (1) This synchronous pinary counter 31 has a count enable terminal E.
The input signal 34 (FIG. 2a) inputted to NL is logic "1".
”, the timing clock signal 36
Binary counting is performed at the rising timing of (b) in the figure. When the input signal 34 is at logic "O°", it is in a disabled state and no binary counting is performed.Therefore, from the output terminal QA of this synchronous binary counter 31, a binary count signal 4l as shown in FIG. 2C is output. It is outputted and inputted to the human input terminal D of the D type flip-flop 32. Here, assuming that the number of bits up to the judgment position is 5 bits, the judgment position pulse 39 as shown in FIG.
All you have to do is enter. Then, by the rising edge 45 of this judgment position pulse 39, the binary count signal 4
The logic “l” of l is captured and the judgment signal 4 is output from the output terminal Q.
2 (e).

If it is predetermined in advance that when this judgment signal 42 is a logic "1", the number of bits "1" is an odd number, and when it is a logic "0", the number of bits "1" is an even number, then in this case, the judgment signal is a logic "1". Therefore, it can be determined that the number of bits "1" is an odd number.

The rising position of this judgment position pulse 39 is input to the input signal 3.
When changing from the 1st bit to the 7th bit of 4,
It can be seen that the determination signal 42 becomes "O" or "1" depending on whether the number of bits "1" included up to the determination position is even or odd.

Note that the logic of the judgment result is based on the D type flip-flop 32.
can be inverted by determining the output signal from the other output terminal d. Furthermore, when determining whether the number of bits "0" in the human input signal 34 is even or odd, the input signal 34 may be inverted using an inverter or the like before being input to the synchronous pinary counter 31. .

〔Effect of the invention〕

As explained above, according to the present invention, the circuit structure can be simplified by eliminating the conventionally used sampling circuit, so that the time and cost required for manufacturing can be reduced. be. Furthermore, in the present invention, binary counting is performed in synchronization with the clock signal only when the human input signal has a predetermined logical value.
Another advantage is that there are fewer malfunctions and higher reliability.

[Brief explanation of drawings]

1 and 2 are for explaining one embodiment of the present invention, of which FIG. 1 is a block diagram showing a parity circuit, and FIG. 2 is a block diagram showing the operation of the parity circuit in FIG. 1. FIG. 3 is a block diagram showing a conventional parity circuit, and FIG. 4 is a timing diagram for explaining the operation of the conventional parity circuit shown in FIG. 3l...Synchronous pinary counter, 32...
...D type flip-flop, 33...Input terminal, 34...Human input signal, 35...
Clock manual terminal, 36... Timing clock signal, 37...
...External output terminal, 38...Judgment position pulse input terminal, 39...
. . . Judgment position pulse signal, 41 . . . Binary count signal, 42 . . . Judgment signal.

Claims (1)

[Claims] Binary counting means that performs binary counting in synchronization with a clock signal of a predetermined cycle only when the input binary signal has a predetermined logical value; Based on the count value output from the counting means, calculate the even number of bits having the predetermined logical value that have been input up to a certain point.
A parity circuit comprising a corresponding signal output means for outputting a signal corresponding to an odd number.