JPH03946B2 - - Google Patents

Description

[Detailed Description of the Invention] (Technical Field) The present invention relates to a PCM in a telemeter measurement device.
The present invention relates to data conversion devices such as encoder devices.

(Prior Art) FIG. 1 is a diagram showing the format of a PCM signal output from a conventional PCM encoder device. In this format, one frame has a fixed length, a frame synchronization code of 1, a frame
It consists of ID (frame identification code) 2 and data 3. After PCM frame #1, PCM frame #2, ... PCM frame #N
are arranged in sequence. Therefore, in such a format, the bit rate, word rate, and frame rate are all constant.

In conventional PCM encoder devices that output data in the format shown in Figure 1, input data is always input like an analog signal, or input data is output as an analog signal.
If the output is from a digital device that has a sufficiently high data transfer capacity compared to the bit rate of the PCM signal, there will be no problem since the data will be updated every frame.

However, in recent telemeter measurement devices, analog signals from sensors and measurement signals from digital devices are primarily processed by a computer, and then the digital output of the same computer is input to a PCM encoder and converted into a telemeter signal. Often transmitted. Even when used in such a telemeter measurement device, there is usually no problem if the data transfer rate from the computer to the PCM encoder device is sufficiently high compared to the bit rate of the PCM signal. Because software is involved, the data transfer rate can be comparable to that of PCM. In this case, the PCM encoder device inputs one block of measurement data from the primary processing computer, composes the data into a PCM frame,
Even after parallel/serial conversion and transmission to the telemeter transmitter are completed, a situation may occur in which the primary processing computer is not ready to output the next block of data. Then, since the PCM signal sent from the PCM encoder device is interrupted, the receiving device that receives the PCM signal cannot achieve bit synchronization when receiving the PCM signal of the next frame. In order to eliminate this problem, conventional PCM encoders usually latch the measurement data transferred from the computer in memory and continue outputting the previous data until the next measurement data is output. It is used in the device.

According to this conventional method, a device that receives telemeter data using a PCM signal also receives unnecessary telemeter data that has not actually been updated. It is not possible for the receiving device to determine whether the transmitted telemeter data is updated, necessary data or previously latched data. Therefore, the receiving device has no choice but to input all received telemeter data. Therefore, in a receiving apparatus in which the received telemeter data is processed by a computer, the required memory capacity of the computer becomes unnecessarily large, and the data processing time of the computer becomes long. Conventional PCM encoder devices have these drawbacks. This drawback is that conventional PCM encoder devices maintain bit synchronization in the receiving device by transmitting data without dropping frames, regardless of whether new data is input. This arose due to the adoption of this method. These drawbacks are not limited to PCM encoder devices. In a data conversion device that outputs data at a bit rate of 2, this is generally unavoidable as long as the second format is a system in which frames are continuous as shown in FIG.

(Object of the Invention) An object of the present invention is to provide a data conversion device that can continuously output bit synchronization information without duplicating information contained in input data.

(Structure of the Invention) The present invention provides a data transmission device that converts data input in a first format into serial data in a second format and outputs the data at a predetermined bit period. a circuit for alternately reading out the data stored in the storage means from the first storage means and from the second storage means; a circuit for generating NULL data; a circuit for converting the data read from the storage means into data in the second format; inputting the NULL data only during a period when the data in the second format is interrupted;
the data in the second format or the data in the second format;
This configuration includes a circuit that outputs NULL data while maintaining bit synchronization.

(Example) Next, the present invention will be described in detail with reference to Examples. FIG. 2 is a diagram showing the format of an output signal of a PCM encoder device according to an embodiment of the present invention.
The PCM frame length is fixed like the conventional PCM frame shown in FIG.
NULL data 4 is output. NULL data 4 is data in which all bits are 0.

FIG. 3 is a block diagram of a PCM encoder apparatus according to an embodiment of the present invention in which the output signal has the format shown in FIG. This embodiment includes telemeter data 50 from a computer for primary processing.
and control signal 51 are input. Data 50 is input block by block, and control signal 51 includes an end-of-transfer signal indicating the end of the block. The central processing unit 7 sends a switching signal 101 synchronized with the transfer end signal to the A/B switch 8 and the timing generation circuit 21. Central processing section 7
The input data 50 is stored in the buffer memory A9 according to the commands stored in the command storage section 6 in advance.
or buffer memory B10, and outputs a switching signal 101. When the switching signal 101 indicates buffer memory A, the A/B switch 8 operates the memory switching switches 11 and 12 to set the contacts of both switches to the A side. The data 50 becomes input data 13 through the input control section 5, and is written into the buffer memory A9 at the timing of the address signal 102 from the central processing section 7. Address signal 102 is data 5
It is synchronized with the timing of 0. Immediately after writing is completed, a switching signal 101 is generated and the A/B
The switch 8 is operated to set the memory changeover switches 11 and 12 to the B side, and the next transferred input data 13 is written into the buffer memory B10. The write operation to the buffer memory is performed by repeating the above operation.

When writing to one buffer memory is completed and the changeover switches 11 and 12 are switched, the address signal supply line is switched from the PCM from the address generator 25.
The data written in the memory is read out at the timing of the PCM address signal 114 and transferred to the parallel/serial converter 16 via the buffer 15. The parallel/serial converter 16 adds a frame ID 117 and a frame sync code 118 generated by a frame ID generator 17 and a frame sync generator 18 to the input data, and serializes the data at the timing of a shift clock 121 from a timing generation circuit 21.
Create a PCM frame and NRZ−L/Biφ−L
(nonreturn to zero level/biphase level) converter 20 and output as an output PCM signal 123 to a telemeter transmitter.

A timing generation circuit 21 receives an output signal 111 from a bit counter 24 operated by a clock 110 from an oscillator 23, and generates a timing signal used in each section. NULL data generator 19
receives the PCM address signal 114, and when the address reaches the maximum address of the buffer memory, that is, when the parallel/serial converter 16 finishes converting all the data in one buffer memory, the data in the next buffer memory is ready. NULL data 119 continues to be generated until it is written (write is completed).
The preparation of the data for the next buffer memory is confirmed by inputting the switching signal 101 to the timing generation circuit 21, clearing the address of the address generator 25 by the timing signal 112, and returning the address signal 114 to address 0, so that it is NULL. The data generator 19 recognizes this. NULL data 119 is
In parallel/serial converter 116, synchronized to the PCM bit by shift clock 121,
It is outputted through the NRZ-L/Biφ-L converter 20.
Buffer memory A9 and buffer memory B10 have the same memory size. This memory size is
For one data block transfer amount of external device,
It only needs to have sufficient capacity, and it is also possible to set an arbitrary frame length by changing the instructions written in the instruction storage section.

In the embodiment shown in FIG. 3, each time a predetermined amount of valid data is input, information on that input data is outputted only once in a predetermined PCM frame, and during periods when data input is interrupted, NULL data is output. is output to maintain bit synchronization between this embodiment and the receiving device. NULL data is received by the receiving device.
Since it can be distinguished from a PCM frame, the computer of the receiving device can process the data by removing NULL data from the received signal.
Therefore, by using this embodiment, unnecessary memory for storing duplicate data can be omitted in the computer of the receiving device, and data processing time in the computer can be shortened. . Furthermore, in this embodiment, since the frame period of the PCM signal 123 is a random arbitrary value, the input data 50 and
The transfer timing of the PCM signal 123 can be mutually set freely, making system design easy.

In addition, in the above-mentioned embodiment, NULL data 4 is
Although the data is assumed to have all bits as 0, it is also possible to use data as all 1 bits.

(Effects of the Invention) According to the present invention, as described in detail above, it is possible to provide a data conversion device that can continuously output bit synchronization information without duplicating information included in input data.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the format of a PCM signal of a conventional PCM encoder device, and FIG. 2 is a diagram showing the format of a PCM signal output from a PCM encoder device according to an embodiment of the present invention.
FIG. 3 is a block diagram of an embodiment of the PCM signal format. 1...Frame synchronization code, 2...Frame
ID, 3...data, 4...NULL data.

Claims (1)

[Claims] 1. A data conversion device that converts data input in a first format into serial data in a second format and outputs the same at a predetermined bit period, wherein first and second data converters alternately store the input data in the order of input. a circuit for alternately reading out the data stored in the storage means from the first storage means and from the second storage means; and a circuit for generating NULL data of the predetermined bit period; A circuit that converts the data read from the storage means into data in the second format, inputs the NULL data only during periods when the data in the second format is interrupted, and converts the data in the second format or the data in the second format. NULL
A data conversion device that includes a circuit that outputs data while maintaining bit synchronization.