JPH0395656A - Bit width variable information processor - Google Patents

Abstract

PURPOSE:To secure the working of a memory having the small bit width by connecting a bus cutting mechanism and selecting a memory bank corresponding to the address value via a decoder when a bus master having the access right has the small bit width. CONSTITUTION:The memory banks 11 and 12 are provided in this example and connected to each other via a bus transceiver. The data bus of the 1st bank 11 is led directly to an 8-bit processor and a 16-bit processor. At the same time, the data bus of the 2nd bank 12 is connected to the 8-bit processor via a bus transceiver 13. The transceiver 13 is set in an enable state via a decoder 14 only when a bus master having the access right is equal to the 8-bit processor and has an access to the address corresponding to the bank 12. In such a constitution, each processor can have accesses to a memory with no consciousness of the fluctuation of the bit width as long as an access is granted by an arbitration circuit to the memory.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention (Industrial Application Field) The present invention relates to a variable bit width information processing device related to a storage device and a communication control device for digital information processing.

(Prior Art) In recent years, with the appearance of microprocessors having data bus widths of 32 bits and 64 bits, cases of bit width conversion between processors having different data bus bit widths have increased. It is important to supply data to these high-speed processors without running out of data in order to take advantage of their high performance, and therefore an efficient bit width conversion method is desired.

In a system where a plurality of bus masters exchange data, when the bit widths of the bus masters differ, the following two methods have conventionally been used.

The first method is to match the bit width of the data bus to the smaller bit width when the bit width of a bus master with a larger bit width can be changed. In this case, although the configuration is simple, the performance of the bus master with a large bit width decreases.

The second method is to match the bit width of the data bus to the larger bit width. In this case, when accessing from a bus master with a small bit width, data is written to a buffer memory with a large bit width and then read/written. This increases the cycle time required for access.

Also, if a bus master with a small bit width has local memory and transfers to or from memory with a large bit width using this method, the bus master with a small bit width will transfer addresses faster than the larger bus master. If it is not updated, the transfer capacity of a bus with a large bit width cannot be fully utilized.

(Problems to be Solved by the Invention) As described above, in a system in which a plurality of bus masters communicate, when the bus masters have different bit widths, the transfer speed is limited by the path master having a small bit width.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a device that prevents transfer speeds from being restricted due to differences in bit widths of bus masters.

[Structure of the Invention] (Means for Solving the Problems) A bus disconnection mechanism that disconnects a plurality of memory banks and a bus master having an access point between the memory banks according to the bit width. and a decoder that selects a memory block corresponding to the address value and bit width size, thereby configuring a variable bit width storage device.

In addition, in a system that has such a variable bit width storage device as the local memory of a bus master with a small bit width and transfers with a bus with a large bit width using an address from the bus master with a small bit width,
In this method, an address conversion mechanism is provided that converts an address from a bus master having a small bit width and supplies the converted address to each memory bank.

A second method is to have a bus master with a small bit width equipped with an address generator that can handle words larger than its own data bus width.

(Function) A plurality of memory banks are connected to a data bus, and a bus disconnection mechanism is placed between these memory banks. Contention when multiple bus masters access memory is arbitrated by an arbitration circuit. Assume that only one bus master is granted access at any given time.

If the bit width of the bus master that has access rights is small, the bus disconnection mechanism is placed in the connected state.

When one memory bank corresponding to the address value is selected by the decoder, it operates as a memory with a small bit width.

On the other hand, if the bit width of the bus master that has access rights is large, the bus disconnection mechanism is placed in a disconnected state. When a plurality of memory banks corresponding to the address value are selected by the decoder, the memory operates as a memory with a large bit width.

Next, consider a system that has a variable bit width storage device as a local memory of a bus master with a small bit width, and uses an address from the bus master with a small bit width to perform transfer with a bus with a large bit width.

If a bus master with a small bit width has a DMA controller, the existing DMA controller has the function of incrementing the address word by word with the bit width of the data bus as one word, but it cannot handle larger bits. It is not assumed that the address will be output with a width of one word. Therefore, an address from a DMA controller with a small bit width cannot be directly used as an address for a large bit width into a variable bit width storage device. The address conversion mechanism converts an address from the DMA controller having a small bit width into an address for a large bit width and supplies the address to each memory bank. Here, if the variable bit width storage device is set in a state where it can be accessed with a large bit width, it becomes possible to perform continuous word-by-word transfer using that bit width as one word.

On the other hand, the DMA controller itself should be equipped with an address generator that can update the address by treating a word larger than its own data bus width as one word, assuming that the bit width will be expanded by a variable bit width storage device. For example, word-by-word transfer can be performed using a large bit width as one word without adding an address translation mechanism as described above.

(Example) Hereinafter, an example of the present invention will be described. FIG. 1 is a diagram showing the configuration of a storage device according to an embodiment of the present invention. As shown in the figure, this embodiment has two memory banks, which are connected via one bus transceiver. The data bus of the first memory bank is directly connected to the 8-bit processor, 1
The data bus of the second memory bank will be connected to the 8-bit processor via a bus transceiver. This bus transceiver is enabled by the decoder only when the bus master having access rights is an 8-bit processor and accesses an address corresponding to the second memory bank. In this case, if each processor is allowed to access memory by the arbitration circuit, then
Memory can be accessed without being aware that the bit width is changing. In this case, the overhead of converting the bit width can be ignored.

FIG. 2 is a diagram showing an embodiment of a bit width variable storage device having an address conversion mechanism. Here, the bit width variable storage device in Figure 1 is used as local memory of an 8-bit processor, a 16-bit processor with a 16-bit wide local memory is connected to the data bus on the 16-bit side, and synchronization is performed between these local memories. Consider the case where data is transferred while taking data.

The address generated by the DMA controller built into the 8-bit processor is converted by the address translation mechanism.
Based on the address, the local memory of the 8-bit processor reads and writes data on the 16-bit data bus. FIG. 3 shows the configuration of the hardware portion of one embodiment of the address translation mechanism. In this example, 2 people 1
The output selector is used to shift the address one bit to the left when the DMA has access rights.

Existing 8-bit wide DMA controllers update addresses in 1 increments. However, when transferring data in 16-bit width, it must be updated in increments of 2. So first, DMA
When setting the start address in the controller initialization program, set the value shifted one bit to the right. The DMA controller updates this address in 1 increments, but the address translation device shifts it to the left by 1 bit, so that the memory is supplied with an address that is updated in 2 increments.

If you replace the above-mentioned DMA controller with an 8-bit DMA controller that uses a counter that can update the address in increments of 2, without using the existing DMA controller, it will be possible to replace it with an 8-bit DMA controller that uses a counter that can update the address in increments of 2. This eliminates the need for right shifts and left shifts using external hardware.

In the above embodiments, 8-bit and 16-bit conversion has been described, but the present invention can be applied to various bit width conversions by changing the number of bus disconnection mechanisms and the number of shifts.

[Effects of the Invention] As described above, by using the present invention, it is possible to eliminate the overhead of bit width conversion in communication between bus masters having different bit widths.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a storage device according to an embodiment of the present invention, FIG. 2 is a diagram showing an embodiment of a bit width variable storage device having an address translation mechanism, and FIG. 3 is a diagram showing an embodiment of a bit width variable storage device having an address translation mechanism. FIG. 2 is a diagram showing the configuration of a hardware portion of an embodiment. 11, 12...Memory bank, 13...Bus disconnection mechanism, 14...Decoder, 23...Address conversion mechanism.

Claims (3)

[Claims] (1) A plurality of memory banks, a bus disconnection means that disconnects the memory banks according to the type of bit width, and a decoder that selects the memory bank corresponding to the address value and the type of bit width. What is claimed is: 1. A variable bit width information processing device comprising: 2. The variable bit width information processing device according to claim 1, further comprising: address conversion means for converting an address from a bus master and supplying the converted address to the memory bank. (3) The variable bit width according to claim 2, further comprising address generation means that is directly connected to the bus master and corresponds to a word larger than the data bus width of the bus master, instead of the address conversion means. Information processing device.