JPH0397375A - Synchronization information correction circuit - Google Patents

Abstract

PURPOSE:To obtain prescribed synchronizing information in proper quanties as synchronizing with a video signal, and to stably execute signal processing using the synchronizing information by comple-menting the lacked synchronizing information by using the periodicity of the synchronizing information. CONSTITUTION:After a synchronizing separation circuit 30 separates a composite synchronizing signal, it separates a vertical synchronizing signal VS by a low pass filter. A signal CP which the logical sum of the regular vertical synchronizing signal VS and the signal AP is outputted from a NOR circuit 40. In the case of the lack of the regular vertical synchronizing signal VS due to drop-out, etc., a monostable multivibrator 50 repeats trigger and clear operations at every one vertical scanning period TF by the signal CP of pulse width r1, and outputs the corrected vertical synchronizing signal of the pulse width r1 to a position where the regular vertical synchronizing signal VS is lacked as the signal CVS.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synchronization information correction circuit that corrects missing synchronization information when a video signal is lost due to dropout or the like.

[Conventional technology]

2. Description of the Related Art Video signal processing devices such as television receivers and magnetic recording and reproducing devices (hereinafter abbreviated as VTR) perform signal processing based on synchronization information included in video signals. Therefore, it is necessary to correctly separate synchronization information from the video signal.

Conventional synchronization separation circuits are devised to reduce synchronization separation errors when separating synchronization information, and such a circuit is disclosed, for example, in Japanese Patent Laid-Open No. 187078/1983.

[Problem to be solved by the invention]

The above conventional technology is a method for compensating for missing synchronization information when synchronization information is lost due to loss of video signals due to dropouts, etc., or disturbance of video signals due to unstable operation of the servo system at the start of playback on a VTR. No consideration was given to this, and there was a problem in that it greatly disturbed signal processing using synchronization information.

An object of the present invention is to compensate for the missing synchronization information when it is lost due to dropout, etc., to output predetermined synchronization information without excess or deficiency in synchronization with the video signal, and to perform signal processing using the synchronization information. It is an object of the present invention to provide a synchronization information correction circuit that can stably perform synchronization information correction.

[Means to solve the problem]

In order to achieve the above object, the present invention makes use of the periodicity of synchronization information, and when synchronization information is missing, corrected synchronization information is output to compensate for the missing synchronization information.

Specifically, a correction synchronization information generation circuit is provided that generates a pulse signal with the same period as the synchronization information included in the video signal.
If the regular synchronization information is separated from the video signal,
The correction synchronization information generation circuit is reset using the separated regular synchronization information, and when the synchronization information is missing, the pulse signal output from the correction synchronization information generation circuit is used as the correction synchronization information. Possible 0 [Operation] When the regular synchronization information is separated from the video signal, the correction synchronization information generation circuit is reset with the regular synchronization information, and is phase-synchronized with the regular synchronization information and synchronized with the regular synchronization information. Operates to generate pulse signals with the same period. Therefore, if the beginning information is missing, the pulse signal output from the corrected synchronization information generation circuit will be output at the same position as the regular synchronization information. Therefore, this pulse signal can be used as correction synchronization information.

As a result, even if regular synchronization information is missing due to dropouts, etc., the missing synchronization information can be compensated for and the desired synchronization information can be obtained in just the right amount and in synchronization with the video signal, allowing signal processing using synchronization information. can be performed stably without erroneous processing.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a synchronization information correction circuit showing a first embodiment of the present invention. FIG. 2 is a waveform diagram of each part of the synchronization information correction circuit shown in FIG. 1.

As an example, a case will be described in which a vertical synchronization signal is lost due to dropout or the like and this is corrected.

In FIG. 1 f, the video signal PBV input from the terminal 10 (FIG. 2 (a)) is ! The signal is supplied to the synchronization separation circuit 30. The synchronization separation circuit 30 separates the composite synchronization signal by comparing the amplitudes using, for example, a conventionally known predetermined threshold value Vr, and then
A low-pass filter separates the vertical synchronization signal ■S, and! The synchronization separation circuit 50 outputs a regular vertical synchronization signal VS (FIG. 2(b)). This normal vertical synchronization signal vS is generated by NOR in the correction synchronization information generation circuit 70.
It is supplied to one input terminal of the circuit 40. Also, NOR
The other input terminal of the circuit 40 is supplied with a signal AP (FIG. 2(f)), which will be described later, and the NOR circuit 40 outputs a signal CP which is the logical addition of the normal vertical synchronization signal vS and the signal AP.
(FIG. 2(C)) is output. This No. 16 CP is the trigger input terminal T+ of the monostable multiviprator 50.

The zero monostable multivibrator 50 is supplied to the clear terminal CR and the trigger input terminal T+. It is triggered by the rising edge of the signal supplied to the output, and operates to output a signal with a pulse width determined by the time constant from the output to the resistor and the capacitor, and at a high level. Also, it is supplied to the clear input terminal CR. When the output signal is at the old level, it operates to bring the signal output from the output terminal Q to the ■ level.

Therefore, when the regular vertical synchronization signal vS is separated, the monostable maltevibrator 50 operates as follows.

When the regular vertical synchronization signal S is separated, the signal CP (Fig. 2 (c)) supplied to the trigger input terminal Too e clear terminal CR of the monostable multi-bicycle brake 5 is the regular vertical synchronization signal. (2) This is a signal with the polarity of S reversed. Therefore, the monostable multiviprator 50 has the above-mentioned signal CPS.
From this, the signal CVS (@Fig. 2 (d)), which is triggered by the falling edge of the regular vertical synchronization signal S and is output from the output terminal, is set to the current level. Fig. 2 (a) 6 shows , one vertical scanning period is TFe regular vertical synchronization signal width j
2 Tv, the period from the falling edge of the normal vertical synchronizing signal vS triggered by the monostable multivibrator 50 to the rising edge of the next normal vertical synchronizing signal ■S is Tr - Tv (Fig. 8g2 (C )). As will be described later, the output pulse width of the monostable multiviprator 50 is TF
- It is set longer than Tv. For this reason, the monostable multivibrator 50 outputs the signal CVS (see Fig. 2 (d) from the output terminal until it is cleared by the rising edge of the next regular vertical synchronization signal
)) is maintained at the m level, and at the same time it is cleared, it operates to set it to the intermediate level. Therefore, the signal CvS is the same as the regular vertical synchronization signal vS.

The signal CvS is supplied to the trigger input terminal T+, 6 of the monostable multivibrator 60. The monostable multivibrator 60 is triggered by the rising edge of the signal supplied to the trigger input terminal T+1, and is connected to the resistor R and the capacitor C.
．． The output terminal Q operates to output a positive polarity signal with a pulse width determined by the time constant of 0. Therefore, when the normal vertical synchronization signal vS is separated, Signal CV8! From this, the pulse width τ, which is phase synchronized with the rising edge of the regular vertical synchronization signal vS,
The signal AP (FIG. 2(e)) is output from the output terminal Q. Note that the pulse width τ, is set so that τ,<Tv.

By the way, the signal AP is supplied to the other input terminal of the NOR circuit 40, but when the regular vertical synchronizing signal vS is separated, τ<Tv, so the signal AP is not the regular vertical synchronizing signal. The output signal CP from the NOR circuit 40 is gated by vS, and the output signal CP from the NOR circuit 40 is the regular vertical synchronization signal ■
If the normal vertical synchronization signal vS is separated from 0 or more, which becomes a signal with S8 polarity inverted,
The monostable multivibrator 50 is activated by the above signal CP,
Since the above trigger and clear operations are repeated, the above signal C
vS is the same signal as the regular vertical synchronization signal vS.

Next, due to dropout etc., the regular vertical synchronization signal ■S
Monostable multivar in case of missing? Preta 50
Explain the operation.

Although not mentioned above, the output pulse width of the monostable multivibrator 50 is determined by TF - τ by resistor & and capacitor C0.
．． Therefore, after the monostable multivibrator 50 is triggered by the above signal CP at the falling edge of the regular vertical synchronization signal vS, the next regular vertical synchronization signal vS is set to 0. If it is missing, the output Yasuko of the monostable multivibrator 50 will also be removed. Signal CV with a pulse width of one TF and a level of ■■■
S (FIG. 2(d)) is output. Then, the monostable multiviprator 60 is triggered by the rising edge of the signal CvS with the pulse width TF - τ, and outputs the signal AP (FIG. 2(e)) with the pulse width τ from the output terminal Q. .

As described above, this signal AP is logically added to the regular vertical synchronizing signal S in the NOR circuit 40, but if the regular vertical synchronizing signal vS is missing, the signal CP (the 2 (C)) is the trigger input terminal T+ of the monostable multiviprator 50. ．． Supplied to clear terminal CR. Therefore, the monostable multivibrator 50 is
A signal CVS with a pulse width of TF-τ and rLJ level
At the same time, it is cleared at the falling edge of the signal CP with the pulse width τ, and after that τ, the signal C is output again.
The signal CVS output from output terminal station 0 is brought to the "river level" until triggered by the rising edge of P.

As is clear from the above explanation, the regular vertical synchronization signal v
If S is missing, the monostable multipipulator 50
repeats the above triggering and clearing operations every vertical scanning period TF using the signal CP with the pulse width τ, and applies a corrected vertical synchronization signal with the pulse width τ to the position where the regular vertical synchronization signal S is missing as the signal CVS. (Fig. 2(d)).

Then, when the regular vertical synchronization signal vS is separated again,
As mentioned above, the monostable multiviprator 50 repeats triggering and clearing operations using the signal CP, which is the polarity inverted version of the regular vertical synchronizing signal S, and the regular vertical synchronizing signal VS
Outputs the same signal from the output terminals.

As a result, even if the regular vertical synchronizing signal S is missing due to dropout, the signal CvS from the output Yasuko of the monostable multivibrator 50 supplied to the terminal 20 is a predetermined signal that compensates for the missing vertical synchronizing signal S. It becomes a vertical synchronization signal, and a signal processing system using a vertical synchronization signal can operate stably without processing errors.

Next, a second embodiment of the present invention will be described using the drawings.

FIG. 3 is a block diagram of a synchronization information correction circuit showing a second embodiment of the present invention, and FIG. 4 is a waveform diagram of each part of the synchronization information correction circuit shown in FIG. wc'5. Note that FIG. 3 has some parts common to FIG. 1, and the common parts are designated by the same reference numerals and detailed explanation thereof will be omitted. Also, similar to the embodiment shown in FIG. 1, a case will be described in which the vertical synchronization signal is lost due to dropout or the like and this is corrected.

In FIG. 3, the video signal P input from the terminal 10
BV (FIG. 4(a)) is supplied to a synchronization separation circuit 306, from which a normal vertical synchronization signal vS (FIG. 4(b)) is separated. The separated regular vertical synchronization signal vS is sent to the monostable multivibrator 10 in the correction synchronization information generation circuit 170.
The signal is supplied to the trigger Yasuko T of 0 and one input terminal of the OR circuit 110. Monostable multivibrator 100
is triggered by the rising edge of the signal supplied to the trigger input terminal T+, and operates to output a positive polarity signal from the output terminal Q, with a pulse width A determined by the time constant of the resistor island and capacitor C. do. Therefore, from the output terminal Q of the monostable multivibrator 100, the rising edge of the normal vertical synchronizing signal VS is synchronized with the pulse width jTi.
A positive polarity signal CL (Fig. 4 (C)) is output, and NO
It is supplied to one input terminal of the R circuit 120.

Further, the other input terminal of the NOR circuit 120 is connected to the decode No. 100 DP (see FIG. 4) which is output from the decoder 150 when the regular vertical synchronization signal
d)) is supplied. The NOR circuit 120 outputs a clear signal CLR (FIG. 4(f)) which is a logical addition of the signal CL and the decode signal DP and whose polarity is inverted.
It is supplied to the clear terminal CR of the counter 160. On the other hand,
The oscillation circuit 14 is connected to the clock terminal CK of the counter 150.
Clock C whose frequency is constant and continuous output from 0
LK (FIG. 4(h)) is supplied. After the counter 130 is reset by the clear signal CLR and the count value is initialized, it starts counting the clock CLK and supplies the count output COP to the decoder 150. Decoder 1
50, when the count value of the counter 150 reaches a predetermined value, a decode signal D having a pulse width of 1 and a positive polarity is generated.
It operates to output P (FIG. 4(d)). however,
Jf snow is the time of one cycle of the clock CLK.

The operations of counter 150 and decoder 150 will be described in detail below.

First, a case where the regular vertical synchronization signal vS is separated will be described.

When the regular vertical synchronization signal ■S is separated, the clear Yasuko CR of the counter 130 contains the regular vertical synchronization signal ■S.
A signal obtained by inverting the polarity of the signal CL (FIG. 4(C)) having a pulse width lτ that is phase synchronized with the rising edge of S is supplied as a clear signal CLR (FIG. 4(F)), and the counter 130 is reset. be done. That is, the counter 130 initializes the count value by the clear signal CLH every vertical scanning period (TF), and when the clear signal CLR is r
The clock CLK% supplied to the clock terminal CK is counted in a certain period of HJ level. The decode value of the decoder 150 is set so that the decode signal DP is output when the counter 130 counts the number of clocks corresponding to TF-j, time 6. Regular vertical synchronization signal■
If S is separated, let lτ, be lτ,〉Aτ!
If the setting is made so that, as shown in FIG. 4(f), the counter 150 starts counting the clock CLK, TF-JT, and then the rising edge of the next regular vertical synchronization signal ■S. It is reset by a clear signal CLR that is phase-synchronized with . At this time, the counter 160 only counts the number of clocks corresponding to TF-1τ, time.
The count value of 30 is a predetermined decode value of the decoder 150 (=Tp − J ft>'rr -Aτ1+”'τ
,〉ノτ,) is not reached. Therefore, when the regular vertical synchronizing signal VS is separated, the decoded signal DP is not output from the decoder 150, and the regular vertical synchronizing signal vS is transmitted through the OR circuit 110 (Q in FIG. 4). Signal CV
S) 0 supplied to terminal 21 Next, due to dropout etc., the normal vertical synchronizer number ■
The operations of the counter 130 and the decoder 150 when S is missing will be explained.

If the regular vertical synchronizing signal S is missing, the counter 130 starts counting and TF-Aτ. Since the signal CLR does not exist, the counter 150 continues counting even after counting the number of clocks corresponding to 'l', p-Jτ, and time. When the counter 130 counts the number of clocks corresponding to TF-Jτ, the decoder 150 outputs a decoded signal DP (FIG. 4(d)) with a pulse width Aτ. The polarity of the decode signal DP is inverted by the NOR circuit 120, and becomes the clear signal CLR (FIG. 4(f)) of the counter 130, which is supplied to the clear terminal CR of the counter 150.
Initialize the count value of 50. And decode signal DP
is at rLJ level (that is, clear signal CLR is at rHJ level)
level), the counter 150 returns to the clock CL.
Start counting K. Therefore, the normal vertical synchronization signal vS
When the vertical synchronizing signal is missing, the decoder 150 outputs a decoded signal DP that compensates for the missing vertical synchronizing signal, and is supplied to the trigger input terminal Tm of the monostable multivibrator 160. The monostable multi-bi break 160 is triggered by the falling edge of the signal supplied to the trigger input terminal Ti, and outputs a positive polarity signal with a pulse width Tv- j f+ determined by the time constant of the resistor & and the capacitor Q+ from the output terminal Q. Operate to output.

Therefore, from the output terminal q of the monostable multivibrator 160, a signal CvP (see FIG.
e)) is output. As shown in FIG. 4(e), the signal CVP serves as a signal to supplement the missing vertical synchronizing signal, is output to the position of the missing vertical synchronizing signal, and is supplied to Yasuko 21 via the OR circuit 110.

By the way, if the regular vertical synchronizing signal vS is separated again after the regular vertical synchronizing signal vS is lost, the counter/counter 1
30 is reset by the clear signal CLR with a pulse width of 1r, and after counting the number of clocks corresponding to Ill, -Δτ2 time, a pulse width of 4τ, which is phase synchronized with the rising edge of the normal vertical synchronizing signal VS, is reset. It is reset by the clear signal CLR (FIG. 4(f)). For this reason,
The decode signal DP is not output from the decode 150,
The counter 130 and the decoder 150 operate again as when the normal vertical synchronization signal vS is separated.

As a result, as shown in FIG. 4(g), the OR circuit 110
If the regular vertical synchronizing signal vS is separated from 6, then the regular vertical synchronizing signal vS becomes the regular vertical synchronizing signal ■S.
If the signal CvP is missing, the correction signal CvP is output as the signal CvS, allowing the signal processing system using the vertical synchronization signal to operate stably without processing errors. Also,
In this embodiment, since the output position of the correction signal CvP can be controlled with an accuracy of one clock of the clock CLK, it is possible to output the vertical synchronization signal corrected for omission at a more accurate position than in the embodiment of FIG.

Next, a fifth embodiment of the present invention will be described with reference to the drawings.

FIG. 5 is a block diagram of a synchronization information correction circuit showing an embodiment of sg3 of the present invention, and FIG. 6 is a waveform diagram of each part of the synchronization information correction circuit shown in FIG. Note that FIG. 5 has some parts in common with FIG. 1, and the common parts are given the same reference numerals and detailed explanation thereof will be omitted.

This embodiment is a recording signal format in which a segment synchronization signal is inserted at the beginning of each segment instead of a vertical synchronization signal in a segment recording system VTR etc. in which a video signal of one vertical scanning period is divided into multiple tracks and recorded. This figure shows a synchronization information correction circuit that can correct when a segment/to synchronization signal is missing due to dropout, etc., even if one segment period is different for each segment when recording and playing back a video signal. It is something. As an example, in a 3-segment recording VTR in which a video signal of one vertical scanning period is divided into six tracks and recorded, two different segment periods (TB, *Tax) are recorded, as shown in FIG. 6(a). A case will be described in which a video signal is recorded and reproduced in a recording signal format in which adjacent segments have different periods.

In FIG. 5, the video signal P input from the terminal 11
BV' (FIG. 6(a)) is supplied to the synchronization separation circuit 5o, and the normal segment synchronization signal SS (FIG. 6(d)) is supplied to the synchronization separation circuit 5o.
are separated. Separated regular segment synchronization signal S
S is the NOR circuit 40 in the correction synchronization information generation circuit 240
is supplied to one input terminal of Further, from the terminal 12, a head switching signal SW is input which controls the timing of switching the video signals reproduced by a plurality of heads.

The head switching signal SW is generated in synchronization with the rotation of a cylinder on which a plurality of heads are mounted, and is a signal that is phase-synchronized with the regular segment/total synchronization signal SS, as shown in Fig. 6~). The signal is supplied to the signal generation circuit 200.

The identification signal generation circuit 200 outputs a signal DSW delayed by a predetermined period of time for the hexagonal switching signal Sw8 so as to have the timing shown in FIG. 6(e), and is supplied to the control terminal C of the selection circuit 230. As is clear from FIG. 6(c), the signal DSW is inserted at the beginning of a segment whose one segment period is Ts1, and at the beginning of a segment whose one segment period is T8t, depending on its polarity. This is an identification signal that identifies the segment synchronization signal that is used.

The selection circuit 230 selects a small number DS based on the signal DSW.
When W is at the rHJ level, the signal supplied to the input terminal A is output to the output terminal D, and when the key signal DSW is at the rLJ level, the signal supplied to the input terminal Bj is output to the output terminal D. It works like that.

Below, six specific operations of the corrected synchronization information generation circuit 240 shown in FIG. 5 will be explained.

First, a case where the regular segment synchronization signal ss is separated will be explained.

As will be described later, when the regular segment synchronization signal ss is separated, the polarity-inverted signal of the regular segment synchronization signal SS8 is output from the NOR circuit 4o as the signal cp' (FIG. 6(e)). and is supplied to the trigger input terminal T+4 and the clear input terminal CR of the monostable multivibrator 210 and the trigger input terminal T+, and the clear input terminal CR of the monostable multivibrator 220. The monostable maltevibrator 210, 220 operates in exactly the same way as the monostable multivibrator 50 of FIG.
The output pulse width of the monostable multivibrator 210 is T8
At t-τ, (τ1 is the output pulse width of the monostable multiviprator 60 and is set to τ,<Tv), the output pulse width of the monostable multiviprator 220 is Ts mar-
τ,6 is set. Now, assuming that the regular segment synchronization signal SSI at the beginning of the first segment is separated as shown in Figure 6 (d), the monostable multiviprator 210, 220 separates the regular segment synchronization signal SSI by the signal CP'. Triggered by the falling edge of SS+, the respective outputs Yazitun. Signal CVS output from louse
I (Fig. 6(f)), signal CVS2 (Fig. 6(g))
is "LJ V f/l/iC fl ro signal CV
S1. CVS2 is the input terminal A. of the selection circuit 230, respectively. The selection circuit 230 is controlled as described above by the signal DSW (FIG. 6(C)) supplied to the control terminal C. Therefore, when the signal DSW reaches the rHJ level in the middle of the first segment, the selection circuit 230 operates to output the signal CvS1 supplied to the input Yasuko A to the output terminal D, so the correction synchronization information generation circuit 240 NOR circuit 40. Monostable multiviprator 210
．． 60 constitutes a circuit similar to the corrected synchronization information generating circuit 70 of FIG. As is clear from the embodiment shown in FIG. 1, by setting the output pulse width of the monostable multibiprator 210 to Tit-τ, the signal DS
During the period when W is at the rHJ level, the correction synchronization information generation circuit 240 operates in an operation mode (hereinafter referred to as mode 1) that corrects the missing percentage of the segment synchronization signal inserted at the beginning of the segment whose one segment period is T'st. Waits for the arrival of the regular segment synchronization signal SS, at the beginning of the second segment. As shown in FIG. 6(d), from the falling edge of the regular segment synchronization signal SSt at the beginning of the first segment that triggered the monostable multiviprator 210, the second
The period up to the rising edge of the regular segment synchronization signal SS at the beginning of the segment is T8t - Tv. As mentioned above, the output pulse width of the monostable multivibrator 210 is set to T8t Tv.
<Ts, - τ, so the monostable multiviprator 210 receives the normal segment synchronization signal SS.
, is separated and the signal CVS1 (see FIG.
f)) It operates to maintain the "L" level and at the same time as clearing rHJ level C, the signal CVS1 is sent from the output terminal Q of the reliable multivibrator 60 via the selection circuit 230 to the above-mentioned regular signal. segment synchronization signal 88,
A signal AP with a pulse width τ, phase-synchronized with the rising edge of
'(FIG. 6(i)) is output and supplied to the other input terminal i of the NOR circuit 40, but since τ1<TV,
The above-mentioned live signal AP' is gated with a regular segment synchronization signal SS, and the output signal cp' from the NOR circuit 40 is
As shown in FIG. 6(e), the regular segment synchronization signal S
S*8 becomes a signal with inverted polarity. Therefore, the monostable multivibrators 210, 220 are cleared by the signal CPI at the rising edge of the normal segment synchronization signal SS, and then the signal SS! is triggered on the falling edge of f and is output from each output terminal 4, us.
'LllcVs 1 , CVS 2jJ - Level "L" again. Therefore, the signal C
The signal CVS 1 output as VS' is the same signal as the regular segment synchronization signal SS, and is supplied to Yasuko 22.

Next, as shown in FIG. 6(e), when the signal DSW reaches rLJ level in the middle of the second segment, the selection circuit 23
0 outputs the signal CVS2 supplied to input terminal B to output terminal D.
Since the correction synchronization information generation circuit 2
40 is a NOR circuit 40. Monostable multivibrator 2
20. 60, the correction synchronization information generation circuit 7 of FIG.
Construct a circuit similar to 0. As is clear from the embodiment shown in FIG. 1, by setting the output pulse ffm'f:Ts*1τ1 of the monostable multibiprator 220, during the period when the signal DSW is at the rLJ level, the correction synchronization The information generation circuit 240 has one segment period of Ts,
An operation mode for correcting the loss of a segment synchronization signal inserted at the beginning of a segment (hereinafter referred to as mode 2)
Then, the regular segment synchronization signal SSm at the beginning of the fifth segment arrives. As shown in FIG. 6(d), from the falling edge of the regular segment synchronization signal SS at the beginning of the second segment that triggered the monostable multiviprator 220, to the regular segment synchronization signal SS at the beginning of the third segment. ．． The period up to the rising edge of Tel! T
It is V. As mentioned above, the monostable multiviprator 22
The output pulse width of 0 is set to Tax - τ1, and T
8! Since the relationship is -Tv<Tit-τ, the monostable multivibrator 220 is cleared at the rising edge of the normal segment synchronization signal Ssm by the signal CP', with the normal segment synchronization signal SS being separated. Until the output Yasuko page. The signal CVS output from
The signal CVS2 (FIG. 6(g)) is maintained at the rLJ level and is set to the "H" level at the same time as it is cleared.
' (Fig. 6 (ω)) and is supplied to the trigger input Yasuko of the monostable multivibrator 60. A signal AP' (Fig. 6(i)) with a synchronized pulse width τ is output, and N
It is supplied to the other input terminal of the OR circuit 40, but τ,
< Tv, the signal AP' is gated with the regular segment synchronization signal SSs, and the output signal CP' from the NOR circuit 40 is the polarity inversion of the regular segment synchronization signal SS++f, as shown in FIG. 6(e). This will be a signal.

Therefore, the monostable multiviprator 210, 220
is cleared by the signal CP' at the rising edge of the normal segment synchronization signal SSm, and then the signal SS
Triggered by the falling edge of fi, the respective outputs 閖子tun. The signals CVS1 and CVS2 output from Wataru 3 are set to the rLJ level again. Therefore, the polarized signal CVS2 output as the signal cvs' via the selection circuit 230
is the same as the regular segment synchronization signal SSm. As a result, when the regular segment synchronization signal ss is separated, the regular segment synchronization signal SS is transmitted from the output terminal D of the selection circuit 230 to the signal cvs' (see FIG. b)) is output.

Next, we will explain the operation of the correction synchronization information generation circuit 240 when the regular segment synchronization signal SS is missing due to dropout or the like from six regular vertical synchronization signals SS4 to the beginning of the fourth and fifth segments. S.S. An example of a case in which the is missing will be explained by Kotori.

After the monostable multiviprator 210, 220 is triggered by the signal CP' at the falling edge of the regular segment synchronization signal SSM at the beginning of the third segment, when the signal DSW becomes rHJ level in the middle of the third segment, As described above, the corrected synchronization information generation circuit 240 is in mode 1 and waits for the regular segment synchronization signal SS4' at the beginning of the fourth segment that arrives after TS+-Tv.

If the regular segment synchronization signal SS4 is missing,
Since the monostable multi-bicycle break 210 is not cleared by the rising edge of the signal SS4, a negative polarity signal with a pulse width of Tst - τ is output from the output terminal Wataru as the signal CVS1 (
It is output as FIG. 6(f)). This signal CVS 1
is the signal cvs'c through the selection circuit 230 in FIG. 6 (h
)) is supplied to the trigger input terminal T+1 of the monostable multiviprator 60, so its output Yasuko Q+ outputs a signal with a pulse width of 1 triggered by the rising edge of the signal cvs' with the pulse width T8+-τ. A signal AP' (FIG. 6(i)) is output. As mentioned above, this signal AP' is converted to the normal segment synchronization signal SS by the NOR circuit 40.
4, but the regular segment synchronization signal SS
4 is missing, the signal CP' (FIG. 6(e)) output from the NOR circuit 40 becomes a signal obtained by inverting the polarity of the signal AP'. Therefore, the monostable multi-bi break 210 outputs a negative polarity signal with a pulse width of Ts, as the signal CVS1, and at the same time outputs a negative polarity signal with a pulse width of τ,
The signal CVS1 output from the output terminal Q4 is set to rHJ until it is cleared at the falling edge of the signal CP' and triggered by the rising edge of the signal CP' after τ1.
Make it a level. As described above, this signal CVS1 passes through the selection circuit 230 and becomes the signal cvs' and is applied to the trigger input terminal T+. of the monostable multiviprator 60. In addition, the normal segment synchronization signal SS4f at the beginning of the missing fourth segment is supplied to the terminal 22, as is clear from FIG. 6(h).
．． becomes.

After the monostable multiviprator 210, 220 is triggered by the rising edge of the signal CP'0) with the pulse width τ, the signal DSW becomes rL in the middle of the fourth segment.
When the J level is reached, as described above, the correction synchronization information generation circuit 240 is in mode 2 and generates the regular segment synchronization at the beginning of the fifth segment that arrives 6 seconds after Tgt# from the falling edge of the correction signal Cvs7. Signal S
Wait for Ss. If the regular segment synchronization signal s83 is missing, the monostable multivibrator 220 will not be cleared by the rising edge of the signal SSs, so the output terminal Q1) will have a negative polarity with a pulse width of 'I'St-τ. The signal is output as a signal CVS 2 (FIG. 6(g)). This prime signal CVS2 becomes a signal CVS' (@6 Figure 5) via the selection circuit 230 and is supplied to the trigger input terminal 'r+,J of the monostable multiviprator 60, so its output terminal Q , the above pulse width Tmu-τ
A signal AP' (Fig. 46 (i)) with a pulse width τ, which is triggered by the rising edge of the signal cvs' of 1, is output.
is logically added to the regular segment synchronization signal SSs, but the regular segment synchronization signal SS. If the signal *AP'f is missing, the signal CP' (FIG. 6(e)) output from the NOR circuit 40 becomes a signal with the polarity of the signal *AP'f inverted. Therefore, monostable multivibrator 220 receives signal C
At the same time when a negative polarity signal with a pulse width of Tit - τ1 is output as VS2, it is cleared at the falling edge of the signal CP' with the pulse width τ, and after that τ, the signal C is cleared again.
until triggered by a rising edge of P'.
The signal CVS2 output from the selection circuit 2 is set to the "}IJ level. As described above, this signal CVS2 is set to the selection circuit 2.
60, the signal cvs' is supplied to the terminal 22 in addition to the trigger input terminal T+1 of the monostable multivibrator 60. The signal CvS≦ is obtained by correcting the regular segment IJ4 signal SSg at a predetermined position.

From the above explanation, even if the regular segment synchronization signal SS is missing, by switching the operation mode of the correction synchronization information generation circuit 240 based on the signal DSWlζ, regular segment synchronization can be achieved even if the one segment period differs depending on the segment. The pulse width τ is at the position where the signal SS is missing.
, can be output as a signal cvs' (FIG. 6, 01)).

Then, when the regular segment synchronization signal SS is separated again, the monostable multiviprator 210, 220 repeats the triggering and clearing operations by the signal CP', which is the polarity inverted version of the regular segment synchronization signal SS, as described above. , the same signal as the regular segment synchronization signal SS is output as the signal cvs'.

As a result, even if one segment period differs depending on the segment, the signal cvs' from the output terminal D of the selection circuit 230 supplied to the terminal 22 will be
This becomes a predetermined segment synchronization signal that compensates for the missing segment synchronization signal, allowing the signal processing system using the segment synchronization signal to operate stably without processing errors. In addition, if there are three or more different segment periods However, like the embodiment shown in Figure @5, it has the same function as the monostable multivibrator 210, but has different segmentation/
By connecting six monostable multivibrators in parallel corresponding to each period and selectively outputting their outputs as appropriate, it is possible to correct the loss of the segment synchronization signal, and this does not depart from the spirit of the present invention. do not have.

Next, a fourth embodiment of the present invention will be described using the drawings.

FIG. 7 is a block diagram of a synchronization information correction circuit showing a fourth embodiment of the present invention, and FIG. 8 is a waveform diagram of each part of the synchronization information correction circuit shown in FIG. Note that FIG. 7 has some parts in common with FIG. 5 and FIG.

Similarly to the embodiment shown in FIG. 5, the tree embodiment is similar to the embodiment shown in FIG. When a signal is lost, the symbol ``i'' indicates a synchronization information generating circuit that can correct this.

In FIG. 7, the video signal P input from the terminal 11
BV' (Fig. 8 (d)) is supplied to the synchronization separation circuit 50, where the regular segment synchronization signal SS (Fig. 8 (d)) is separated. Separated regular segment synchronization signal SS
is supplied to the trigger input terminal T+*b of the monostable multiviprator 100 in the corrected synchronization information generation circuit 330 and to one input terminal of the OR circuit 110. The monostable multiviprator 100 uses the regular segment synchronization signal SS
, and a positive polarity signal CL' (FIG. 8(e)) with a pulse width τ that is phase-locked with the rising edge of the regular segment synchronization signal SS is output from its output terminal Q. This signal CL' is then supplied to one input terminal of the NOR circuit 120. In addition, the NOR circuit 120
As will be described later, the other one of the input signals is a decode signal DP' (Q1 in FIG. 8) which is output from the output terminal D of the selection circuit 230 when the regular segment synchronization signal SS is missing.
) is supplied. From the NOR circuit 120, the above signal C
A clear signal CLR' (FIG. 8(j)) obtained by logically adding L' and decode signal DP' and inverting the polarity is output and supplied to the clear terminal CR of the counter 30. On the other hand, the clock terminal CK of the counter 30 is supplied with a constant and continuous clock CLK output from the oscillation circuit 140.

After the counter 30 is reset by the clear signal CLR' and the count value is initialized, it starts counting the clock CLK, and the decoder A! 510, decoder B52
0 6 provides the counting output cop'+. Decoder A
310 and decoder B 320 respectively have counter 1
When the count value of 50 reaches a predetermined value, the pulse width becomes lτ
, and positive polarity decode signal DPA (Fig. g8 (f))
, DPB (FIG. 8 0)). However, Aτ is the time of one cycle of the clock dLK. On the other hand, the signal shown in Figure @5 is input from the terminal 12 and supplied to the identification signal generation circuit W&200.

The identification signal generation circuit 200 outputs a signal DSW which is the head switching signal SW delayed by one predetermined time so as to match the timing shown in FIG. 8(c), and is supplied to the control terminal C of the selection circuit 230. As is clear from FIG. 8g8 (c), the signal DSW is inserted at the beginning of the segment whose one segment period is T8+ and at the beginning of the segment whose one segment period is T8t, depending on its polarity. This is an identification signal that identifies the segment synchronization signal.

The selection time @230 is based on the signal DSW, and the signal DS
When W is at the rHJ level, the decoded signal DPA supplied to the input terminal A is used; when the signal USW is at the rLJ level, the decoded signal DP is supplied to the input terminal B.
B is output from output terminal D as decoded signal DP'.

Hereinafter, first, a case where the regular segment synchronization signal SS is separated will be explained.

If the regular segment synchronization signal SS is separated,
The clear Yasuko CR of the counter 150 contains the above-mentioned signal CL' (FIG. 8(e)') whose phase is synchronized with the rising edge of the normal segment synchronization signal SS. (j)) and the counter 130 is reset. Now, Figure 8 (d
), if the regular segment synchronization signal ssI at the beginning of the first segment is separated, the counter/counter 15
0 initializes the count value with the clear signal CLR' which is phase synchronized with the rising edge of the regular segment synchronization signal SS, and is supplied to the clock Yasuko CK during the period when the clear signal CLR' is at the rHJ level. Ta clock ji! Count LK.

By the way, in the middle of the first segment, the signal DSW becomes rHJ.
When the level is reached, the selection circuit 230 operates to output the decoded signal DPA supplied to the input terminal A to the output terminal D6, so the fine synchronization information generation circuit 530
circuit 40, counter 13o. The decoder 510l constitutes a circuit similar to the corrected synchronization information generation circuit 170 in FIG. Therefore, as is clear from the actual example in Figure 5, C.
Decoded value 'i of decoder A510: Ta+Aτ8
# If this is set, the correction synchronization information generation circuit 4530 is in the operation mode (mode 1) that corrects the omission of the segment synchronization signal inserted at the beginning of the segment whose one segment period is T8, and Wait for the arrival of the regular segment synchronization signal SS at the beginning of the segment synchronization signal SS.

Regular segment synchronization signal SS at the beginning of the second segment
! is separated, by setting lτI so that Δτ2〉At, as shown in FIG. 8(j)9,
After T8t'τ after the counter 150 starts counting the clock CLK, the clear signal CLR is phase-synchronized with the rising edge of the normal segment synchronization signal SSI.
' is reset. At this time, the counter 150 is T8
Since only the number of clocks corresponding to 6 hours is counted, the counted value of the counter 150 is the same as that of the decoder A310.
A predetermined decode value of ( ”T8+−J rt>T8
+ j f, , ゜．゜Jτ,〉lτI), and the decode signal DPA is not output from the decoder A310. Therefore, as shown in FIG. 8(g)) and is supplied to the terminal 23.

The counter 130 receives the regular segment synchronization signal 88.
．． After being reset by the clear signal CLR' phase-synchronized with the rising edge of , the clock CLKf is counted again during the period when the clear signal CLR' is at the rHJ level. and,
When the signal DSW reaches rLJ level in the middle of the second segment, the selection circuit 230 operates to output the decoded signal DPB supplied to the input terminal B to the output terminal D. Therefore, the correction synchronization information generation circuit 330 operates as a NOR circuit. 40. The counter 150 and the decoder B520 cause the decoder B3 to
If the decode value of 20 is set to T's* + j ft, in the operation mode (mode 2) that corrects the loss of the segment synchronization signal inserted at the beginning of the segment whose one segment period is Ts, the third Wait for the arrival of the regular segment synchronization signal SSs at the beginning of the segment.

Regular segment synchronization signal SS at the beginning of the third segment
, is separated, as shown in No. 81a(j), the counter 150 starts counting the clock CLK and then Tl1! 'τ, and later, it is reset by the clear signal CLR' which is phase-synchronized with the rising edge of the normal segment synchronization signal SSs. At this time, the counter 130
only counts the number of clocks corresponding to Tst - j r, time, so the counting of the counter 150 is based on the predetermined decoded value of the decoder B320 (=Ts! - τt >
'rst-τI * ``r,〉ノ'' talc is not reached, and the decoded signal DPB is not output from the decoder B 320. Therefore, as shown in FIG. However, the decoded signal DP' is not outputted, and the regular segment/decode synchronization signal SS is supplied to the terminal 23 via the OR circuit 110 as the signal cvs' (FIG. 8(G)).

As a result, when the regular segment synchronization signal SS is separated, the output Yasuko D of the selection circuit 230 does not output the decode signal DP', and the regular segment synchronization signal S
S becomes a signal cvs' and is output from the OR circuit 110.

Next, the correction synchronization information generation circuit 3 when the regular segment/to synchronization signal SS is missing due to dropout etc.
30 is performed using the regular synchronization signal SS.30 at the beginning of the fourth and fifth segments. ．． An example in which SS, is missing will be explained.

The counter 130 is reset by the clear signal CLR' which is phase-locked to the rising edge of the previous regular segment synchronization signal SSm of the fifth segment, and is again clocked by the clock CL.
After starting counting K, signal D is activated in the middle of the 5th segment.
When SW reaches rHJ level 6, the correction synchronization information generation circuit 350 is in mode 1 and T81-' as described above.
τ, the regular segment synchronization signal SS.T at the beginning of the fourth segment that arrives later. wait. If the regular segment synchronization signal SS4 is missing, the counter 130 starts counting, and even if time T8+-j has passed, the clear signal remains in phase synchronization with the rising edge of the regular segment synchronization signal SS. Since signal CLR' is not present, counter 150
continues counting even after counting the number of clocks corresponding to Ts, - Δτ2 time. And Kau/ta 130
is Ts+'τ! A pulse is sent from the decoder A310 to indicate that the number of clocks corresponding to the time has been counted! , if, is output, and the decode signal DP' (toward FIG. 8) is output via the selection circuit 230.
becomes. The polarity of the decode signal DP' is inverted by the NOR circuit 120, and the clear signal CLR' (8th
(j)), and the count value of the counter 150 is initialized. Then, when the decode signal DP' reaches the rLJ level (that is, the clear signal CLR' reaches the rHJ level),
The counter 130 starts counting the clock CLK again. Therefore, when the regular segment synchronization signal 884 is missing, the selection circuit 230 outputs a decode signal DP' that compensates for the missing segment synchronization signal, and the trigger input terminal T of the monostable multiviprator 160 outputs the decode signal DP' that compensates for the missing segment synchronization signal. supplied to The monostable multivibrator 160 is triggered by the falling edge of the decoded signal DP' and outputs the output terminal Qs.
A positive signal CVP'(1<8 in Figure (i)) with a pulse width Tv-1t+(7) is output.

As shown in FIG. 8(i), the signal cvp' is output to the position of the missing segment synchronization signal, serves as a signal to supplement the missing segment synchronization signal, and is passed through the OR circuit 110 to the signal cvs' (see FIG. (see below) and is supplied to the terminal 25.

In this way, the missing regular segment synchronization signal SSa
is corrected, and the counter 150 receives the decoded signal DPA.
After being reset by the clear signal CLR' based on the clock CLK and restarting counting of the clock CLK, when the signal DSW reaches the rLJ level in the middle of the fourth segment, as described above,
The correction synchronization information generation circuit 530 generates Tst in the mode 2 state.
It waits for the regular segment synchronization signal SS at the beginning of the fifth segment, which arrives after Iτ1. When the regular segment synchronization signal SS@ is missing, the counter 150 starts counting operation and remains in phase synchronization with the rising edge of the regular segment synchronization signal SSs even after a period of time Tst'τ. Since the clear signal CLR' does not exist, the counter 150 continues counting even after counting the number of clocks corresponding to Tax lτ and the time number. Then, when the counter 130 counts the number of clocks corresponding to Tax-no τ and time l, the clock pulse width A is output from the decoder B320.
The decode signal DPB (FIG. 8 0)) of T, is output,
It becomes a decoded signal DP' (FIG. 8, 5)) through the selection circuit 230. The decode signal DP' is provided by the NOR circuit 120.
The polarity is inverted by the clear signal CLR' of the counter 130.
(FIG. 8(j)), and the count value of the counter 150 is initialized. Then, when the decode signal DP' reaches the rLJ level (that is, the clear signal CLR' reaches the rHJ level), the counter 150 starts counting the clock CLK again. Therefore, even if the regular segment synchronization signal SSl is missing, the selection circuit 230 outputs the decode signal DP' that covers the missing segment synchronization signal, and the trigger input terminals T-, 6 of the monostable multiviprator 160
This is supplied. The monostable multiviprator 160 is triggered by the falling edge of the decoded signal DP', and outputs a positive polarity signal c with a pulse width Tv-jτ1 from the output terminal Q.
vp'< FIG. 8(i)) is output. signal cvp'
As shown in FIG. 8(i), the signal f. is output to the missing segment synchronization position to compensate for the missing segment synchronization signal. r Q, signal CVS via OR circuit 1108
'(FIG. 8(g)), and the terminal 254 is supplied.

From the above explanation, even if the regular segment synchronization signal SS is missing, by switching the operation mode of the correction synchronization information generation circuit 550 based on the signal DSW, even if the one segment period differs depending on the segment, the regular segment A pulse I [T
The corrected vertical synchronization signal of v-jτ1 is the signal CVS' (8th
It can be output as a figure (g)).

Then, when the regular segment synchronization signal SS is separated again, the counter 130 uses the clear signal CLR' having a pulse width τ, phase synchronized with the rising edge of the regular segment synchronization signal SS, as described above. Although the reset and counting operations are repeated 8 times, the defood signal DP' is not output from the selection circuit 230, and the regular segment synchronization signal SS is output.
becomes the signal cvs' through the OR circuit 110 and outputs it to terminal 2.
5.

As a result, even if one segment period differs depending on the segment, the signal cvs' supplied to the terminal 23
When the regular segment synchronization code SS is missing due to dropout etc., the missing segment synchronization signal is supplemented with the correction signal cvp' to become a predetermined segment synchronization signal, and the signal processing system using the segment synchronization signal can be erroneously It can operate stably without processing. Also,
In this embodiment, since the output position of the correction signal cvp' can be controlled with an accuracy of one clock of the clock CLK, the fifth
It is possible to output a segment-same JtA signal that has been corrected for missing positions more accurately than the illustrated embodiment.

Note that even if there are five or more different segment periods, similar to the embodiment shown in Figure @7, decoders that have the same function as decoder A310 and that correspond to the different segment periods can be connected in parallel. , by appropriately selecting and outputting these outputs, it is possible to correct the omission of the segment synchronization signal, which does not depart from the gist of the present invention.

Further, in the embodiments shown in FIGS. 5 and 7, the signal DS that controls the selection circuit 230 from the head switching signal SW
Although the above-mentioned signal DSW is generated, the signal DSW is not limited to the head switching signal SW, and the signal DSW can be similarly generated by using a signal representing the rotational phase of the head, without departing from the spirit of the present invention.

Furthermore, in the embodiments shown in FIGS. 5 and 7, if the periods of each segment are all equal, the missing segment synchronization signal can be corrected by the embodiments shown in FIGS. 1 and 5. It's obvious.

Furthermore, a vertical synchronization signal. Not limited to sekumet/to synchronization signals,
As long as the periodic information has periodicity, the omission can be corrected in the same manner as in the above embodiment, and this does not depart from the spirit of the present invention.

〔Effect of the invention〕

According to the present invention, even if synchronization information is missing due to dropout or the like, the periodicity of the synchronization information is used to compensate for the missing synchronization information, and predetermined synchronization information is obtained in synchronization with the video signal without excess or deficiency. Therefore, signal processing using synchronization information can be stably performed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention;
The figure is a waveform diagram of each part, FIG. 3 is a block diagram showing the second embodiment of the present invention, FIG. 4 is a waveform diagram of each part, and FIG. 5 is a block diagram showing the @3 embodiment of the present invention. 6 is a waveform diagram of each part, FIG. 7 is a block diagram showing an embodiment of @4 of the present invention, and FIG. 8 is a waveform diagram of each part. 10, 11. 12...Input terminals 20, 21
, 22. 25... Output terminal 30... Synchronous separation circuit 50, 210, 220... Monostable multivibrator 130... Counter 140... Oscillation circuit 150, 310, 320... Decoder 2
00...Identification signal generation circuit 230...Selection circuit block 1 Figure

Claims (1)

[Claims] 1. In a video signal processing device in which the cycle of synchronization information contained in a video signal is single and performs signal processing based on the synchronization information, the synchronization information contained in the video signal is a separating means (30) for separating; a logical addition circuit (40) whose first input is the synchronization information separated by the separating means (30); T_F is the period of the separated synchronization information; time width of synchronization information,
Assuming that τ_1 is a constant having a unit of time such that τ_1<T_V, it is reset in response to the output of the logic adder circuit (40), and in phase synchronization therewith, the time width T_F−τ_
a first generating means (50) that generates a signal with a time width τ_1, and a second generating means (60) that generates a signal with a time width τ_1 in phase synchronization with the output of the first generating means (50); and the output of the second generating means (60) is connected to the logical addition circuit (
40), and the first generating means (50)
A synchronization information correction circuit characterized in that corrected synchronization information is obtained from the output of. 2. In a video signal processing device in which the synchronization information contained in the video signal has a single cycle and performs signal processing based on the synchronization information, a separating means (30 ), and a first generating means (10) for generating a signal of a predetermined time width in phase synchronization with the synchronization information separated by the separating means (30).
0), and a counting circuit (130) that counts clock signals of a predetermined frequency.
), and a detection means for detecting that the count value of the counting circuit (130) has reached a value corresponding to time T_F - Δτ_2, where T_F is the period of the separated synchronization information and Δτ_2 is the period of the clock signal. (150) and the detection means (15
a second generating means (160) that generates a signal of a predetermined time width in phase synchronization with the output of the detecting means (150);
100) and the output of the first logical addition circuit (
120), and a second logic addition circuit (110) for logically adding the synchronization information separated by the separation means (30) and the output of the second generation means (160), The count value of the counting circuit (130) is initialized by the output of the logic addition circuit (120), and the second logic addition circuit (110)
A synchronization information correction circuit characterized in that corrected synchronization information is obtained from the output of. 3. The period of synchronization information included in the video signal is n (n is 2
a video signal processing device that performs signal processing based on the synchronization information, comprising: separating means (30) for separating the synchronization information included in the video signal from the video signal; A logical addition circuit (40) which receives the separated synchronization information as a first input, and Ti (i=1, 2,
..., n) is the period of the separated n different synchronization information, T_V is the time width of the synchronization information, and τ_1 is τ_1<
As a constant having a unit of time T_V, it is reset in response to the output of the logic adder circuit (40), and in phase synchronization therewith, generates a signal with a time width Ti-τ_1 according to each period Ti of the synchronization information. n independent generating means (210, 220), and a selection means (230) for selecting and outputting one output as appropriate from the outputs of the n independent generating means (210, 220).
and the time width τ_ in phase synchronization with the output of the selection means (230).
generating means (60) for generating a signal of 1; the output of the generating means (60) is applied to the logical addition circuit (40);
A synchronization information correction circuit, characterized in that the synchronization information is obtained as a second input of the selection means (230), and corrected synchronization information is obtained from the output of the selection means (230). 4. The period of synchronization information included in the video signal is n (n is 2
a video signal processing device that performs signal processing based on the synchronization information, comprising means (30) for separating the synchronization information included in the video signal from the video signal; and separating from the separation means (30). a first generating means (10
0), and a counting circuit (130) that counts clock signals of a predetermined frequency.
), Ti (i=1, 2,..., n) is the cycle of the n different synchronization information separated above, and Δτ_2 is the cycle of the clock signal, the count value of the counting circuit (130) is the above n independent detection means (310, 320) for detecting that the synchronization information has reached a value corresponding to time Ti - Δτ_2 according to each period Ti, and the n independent detection means (3
10, 320), and a second generating means (160) that generates a signal of a predetermined time width in phase synchronization with the output of the selection means (230). ), the output of the selection means (230) and the first generation means (
100) and the output of the first logical addition circuit (
120); and a second logic addition circuit (110) for logically adding the synchronization information separated by the separation means (30) and the output of the second generation means (160); The count value of the counting circuit (130) is initialized by the output of the first logic addition circuit (120), and corrected synchronization information is obtained from the output of the second logic addition circuit (110). Features a synchronization information correction circuit. 5. A generating means (200) for identifying the period of the synchronization information and generating an identification signal accordingly;
5. The synchronization information correction circuit according to claim 3 or 4, wherein the selection means (230) is controlled in accordance with the output of the synchronization information correction circuit (200).