JPH0399454A - C-mos gate array - Google Patents
C-mos gate arrayInfo
- Publication number
- JPH0399454A JPH0399454A JP1236025A JP23602589A JPH0399454A JP H0399454 A JPH0399454 A JP H0399454A JP 1236025 A JP1236025 A JP 1236025A JP 23602589 A JP23602589 A JP 23602589A JP H0399454 A JPH0399454 A JP H0399454A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- pad
- power supply
- gate array
- center
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 13
- 229910052782 aluminium Inorganic materials 0.000 description 13
- 238000003491 array Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Dram (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】 ［産業上の利用分Ｗ］ 本発明は、チップ中央に電源専用パラ た０−ＭＯ８ゲートアレイに関する。[Detailed description of the invention] [Industrial usage W] The present invention has a dedicated power supply param- eter in the center of the chip. 0-MO8 gate array.
ドを配し
［従来の技術］
従来の０−Ｍ０３ゲートアレイにおいては、高集積・大
規模ゲート化に伴い、チップ面積が大きくなる傾向にあ
るが、電源供給はチップ周囲のパッドからだけであった
。[Prior art] In conventional 0-M03 gate arrays, the chip area tends to increase with the increase in integration and large-scale gates, but power supply is not limited to pads around the chip. Ta.
［発明が解決しようとする課題］
前述の従来技術では、電源供給はチップ周囲のパッドか
らだけであるために、チップ中央への電源供給が不安定
であると言う問題点かありた。そこで、本発明は従来の
このような問題点を解決するため、チップ周囲のパッド
からの電源供給と併せて、チップ中央に電源専用パッド
を配し、チップ中央への電源供給を安定して行なうこと
を目的とする。[Problems to be Solved by the Invention] In the above-mentioned conventional technology, power is supplied only from the pads around the chip, so there is a problem in that the power supply to the center of the chip is unstable. Therefore, in order to solve these conventional problems, the present invention provides power supply from the pads around the chip and also arranges a dedicated power pad in the center of the chip to stably supply power to the center of the chip. The purpose is to
［護国を解決するための手段］
本発明の０−Ｍ０ｉ９ゲートアレイは、ａ） 半導体集
積回路における、
ｂ） チップ周囲のパッドと、
Ｃ） セル配置領域と、
ｄ） 配線領域と、
ｅ） チップ中央の電源専用パッド
とからなることを特徴とする。[Means for solving the problem of national protection] The 0-M0i9 gate array of the present invention can be applied to a) a semiconductor integrated circuit, b) a pad around the chip, C) a cell placement area, d) a wiring area, and e) a chip. It is characterized by consisting of a central power supply pad.
［実施例］
第１図は、本発明の実施例における０−Ｍ０！９ゲート
アレイの全体図である。構成は、チップ中央に配置する
電源専用パッド１と、チップ周囲のパッド２．セル配置
領域３．配線領域４からなるチップ中央の電源専用パッ
ドは、セル配置領域上に置（、第２図は電位に着目した
アルミ１層とアルミ２層の平面図である。チップ周囲の
任意のパッド５，６をｖｓｓおよび、ＶＤＩＩの電位に
することにより、チップ周囲のアルミ配線７，８かも、
チップ内のＸ方向のアルミ１層配線９とＸ方向のアルミ
２層配線１０にそれぞれの電位が与＾られる。チップ面
積が大きくなると、チップ内のアルミ１層配線とアルミ
２層配線が長くなり、チップの中央部への電源供給が不
安定になる。そこで、チップ中央に電源専用のパッド１
０１を配置して、そのパッドから直接チップ内のアルミ
１層配線とアルミ２層配線に電源を供給する。[Embodiment] FIG. 1 is an overall diagram of a 0-M0!9 gate array in an embodiment of the present invention. The configuration consists of a power supply dedicated pad 1 placed in the center of the chip, and pads 2 around the chip. Cell placement area 3. A pad dedicated to power supply at the center of the chip consisting of the wiring area 4 is placed on the cell placement area (Figure 2 is a plan view of the first aluminum layer and the second aluminum layer focusing on the potential. Any pads 5 around the chip, By setting 6 to the potential of vss and VDII, the aluminum wiring 7 and 8 around the chip can be
Potentials are applied to the first-layer aluminum wiring 9 in the X direction and the second-layer aluminum wiring 10 in the X direction within the chip. As the chip area increases, the first-layer aluminum wiring and the second-layer aluminum wiring within the chip become longer, making the power supply to the center of the chip unstable. Therefore, a pad 1 dedicated to power supply is placed in the center of the chip.
01, and power is directly supplied from the pad to the first-layer aluminum wiring and the second-layer aluminum wiring within the chip.
［発明の効果］
本発明は、０−ＭＯＳゲートアレイにおいてチップ中央
に電源専用パッドを配した構成としたので、チップ面積
の増大においても、チップ全体にわたり、安定した電源
供給をおこない、高周波動作においても、電位の低下に
よる、内部回路の誤動作が、防げるという効果がある。[Effects of the Invention] The present invention has a configuration in which a dedicated power supply pad is arranged in the center of the chip in a 0-MOS gate array, so even when the chip area increases, a stable power supply can be provided throughout the chip, and high frequency operation can be achieved. This also has the effect of preventing malfunctions of internal circuits due to potential drops.
また、チップ中央の電源専用パッドは、セル配置領域上
に配置したことにより、セル相互をつなぐ配線の自由度
に対し、ての制約はない。Furthermore, since the power supply dedicated pad at the center of the chip is arranged on the cell arrangement area, there is no restriction on the degree of freedom of wiring connecting cells to each other.
第１図は実施例を示す全体図。
１・・・・・・・・・電源専用パッド
２・・・・・・・・・チップ周囲のパッド３・・・・・
・・・・セル配置領域
４・・・・・・・・・配線領域
第２図は実施例を示す平面図。
５・・・・・・・・・任意のＶＥＪＢパッド６・・・・
・・・・・任意のＶＤＤパッド７・・・・・・・・・チ
ップ周囲のアルミ配線８・・・・・・・・・チップ周囲
のアルミ配線９・・・・・・・・・チップ内のアルミ配
線０・・・・・・・・・チップ内のアルミ配線以FIG. 1 is an overall view showing an embodiment. 1...Pad for power supply 2...Pad around the chip 3...
. . . Cell arrangement area 4 . . . Wiring area FIG. 2 is a plan view showing an embodiment. 5...... Any VEJB pad 6...
・・・・・・Arbitrary VDD pad 7・・・・・・Aluminum wiring around the chip 8・・・・・・Aluminum wiring around the chip 9・・・・・・・・・Chip Aluminum wiring inside 0...... Aluminum wiring inside the chip
Claims (1)
ゲートアレイ。[Claims] a) In a semiconductor integrated circuit, a C-MOS comprising: b) a pad around the chip; c) a cell placement area; d) a wiring area; and e) a pad dedicated to power supply at the center of the chip.
gate array.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1236025A JPH0399454A (en) | 1989-09-12 | 1989-09-12 | C-mos gate array |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1236025A JPH0399454A (en) | 1989-09-12 | 1989-09-12 | C-mos gate array |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0399454A true JPH0399454A (en) | 1991-04-24 |
Family
ID=16994651
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1236025A Pending JPH0399454A (en) | 1989-09-12 | 1989-09-12 | C-mos gate array |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0399454A (en) |
-
1989
- 1989-09-12 JP JP1236025A patent/JPH0399454A/en active Pending
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