JPH0399548A - Psk demodulation system - Google Patents

Abstract

PURPOSE:To make a PSK demodulator small-sized and high-performance by providing a bit synchronizing loop, which digitally extracts a synchronizing clock, in parallel with a costus type demodulation loop which demodulates the phases of digitized two-phase PSK signals. CONSTITUTION:A PCM-PSK base band signal passes an LPF 2 and an AGC circuit 3 and is supplied to an A/D converter 4 and is converted to a digital signal. A sampling clock at this time is supplied from a clock generating synthesizer 1. The signal is controlled in a coherent AGC circuit 5 in accordance with PSK demodulation data detected by an AGC operation/clock discriminator 17 and is subjected to PSK demodulation by an I component detector 6 and a Q component detector 7. The phase error from a bit synchronism error detector 9 is given to a numerically controlled oscillator 15 through a loop filter 13 in parallel with the PSK demodulating operation, and the sampling frequency is changed to acquire the bit synchronism.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a PSK demodulation method, and in particular to a PSK demodulation method (related to this .

[Conventional technology]

The PCM-PSK-PM method is used in lines that transmit telemetry signals from artificial satellites to control stations on the ground, in which the carrier wave is phase-modulated using a signal obtained by two-phase PSK modulating the subcarrier with a PCM signal, which is a telemetry signal. . The received signal is phase demodulated to become a PCM-PSK baseband signal, and is further subjected to PSK demodulation and bit synchronization.

Conventionally, in this type of PSK demodulation method, an independent PSK demodulation circuit and a bit synchronization circuit are constructed from analog circuits, and the input PCM-PSK baseband signal is processed as a PCM baseband signal by the PSK demodulation circuit. After phase detection, the signal is output to a bit synchronization circuit, which shapes the waveform of the PCM baseband signal and detects a synchronization clock.

These operations are sequential operations such as PSK demodulation and then bit synchronization.

[Problem to be solved by the invention]

Since the conventional PSK demodulation method described above is composed of analog circuits, there is a factor of instability, and it takes a lot of time to adjust and test the performance of each of the PSK demodulation circuit and the bit synchronization circuit. Moreover, it has the disadvantage that PCM-PSK demodulation cannot be achieved unless it is input to the bit synchronization circuit after passing through the PSK demodulation circuit, and it takes time to extract the signal after bit synchronization for signals with slow communication speeds such as bit rate. There is a drawback that it takes a long time.

[Means to solve the problem]

The PSK demodulation method of the present invention includes an A-D converter that digitizes a two-phase PSK signal, a Costas-type demodulation loop that digitally demodulates the phase of the digital signal output from this A-D converter, and A bit synchronized loop is provided in parallel with the loop and digitally extracts a synchronized clock from the digital signal output from the A/D converter.

The PSK demodulation system of the present invention may include an automatic gain control circuit that controls the level of the digital signal output from the A-D converter based on the demodulated data component obtained in the demodulation loop.

The bit-locked loop provided in the PSK demodulation method of the present invention includes a numerically controlled oscillator that outputs the synchronized clock by being phase-controlled by a control signal, and a numerically controlled oscillator that outputs the digital signal outputted by the AD converter. A multiplication and addition circuit for phase error detection that performs synchronous detection at the timing of the center bit of the two-phase PSK signal based on the synchronization clock, and a digital loop filter that generates the control signal from the output signal of this multiplication and addition circuit. There may be.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

1 is a synthesizer for clock generation, 2 is a low-pass filter,
3 is an automatic gain control (AGC) circuit, 4 is an A-D converter, 5 is a coherent AGC circuit, and 6 is a component detector for PSK demodulation, which is composed of a digital multiplication and addition circuit.
7 is a Q component detector for PSK demodulation, which is composed of a digital multiplication and addition circuit; 8 is a demodulation error detector that detects the PSK demodulation phase error, which is composed of a digital multiplication and addition circuit; 9 is a bit synchronization error detector. 10 is a SIN waveform generator and a ROM
11 is a CO8 waveform generator r(OM), 12 is a digital loop filter for the PSK demodulation loop, 13 is a digital loop filter for the bit synchronization loop, and 14 is a PSK demodulation loop filter. A numerically controlled oscillator for fJE tuning, 15 a numerically controlled oscillator for bit synchronization, 16 a timing generator, 17 an AGC calculation/lock determination device, and 18 a DA converter.

The PCM-PSK baseband signal that has been subjected to two-phase PSK modulation is passed through a low-pass filter 2 whose cutoff frequency is set by the PSK subcarrier frequency to improve the S/N ratio of the input signal, and the signal level (noise) is improved by the AGC circuit 3. ) is made constant, and then the analog signal is converted into a digital signal by the A-D converter 4. The sampling clock at this time is supplied from the clock generation synthesizer 1, and the sampling rate is an integer (2 to the N1 power) times the PSK subcarrier frequency.

The clock generation synthesizer 1 has an externally set P
A PSK sampling clock and a bit rate sampling clock are generated based on the SK subcarrier frequency and bit rate information.

In the coherent AGC circuit 5, the AD output data is controlled according to the magnitude of the PSK demodulated data component detected by the AGC calculation/lock determination unit 17.

■The PCM-PSK sampling data input to the component detector 6 is phase-detected by parallel data corresponding to the SIN wave (in-phase component of the PSK subcarrier) output by the SIN waveform generator 1o, and the signal is PSK demodulated and demodulated. (opposite phase) becomes a signal component and is output.

On the other hand, the PCM-PSK sampling data input to the Q component detector 7 is the C
Phase detection is performed using parallel data corresponding to the O8 wave (orthogonal component of the PSK subcarrier), and a PSK demodulated Q (orthogonal) signal component is output.

The above phase detection uses the PCM-PSK sampling data from the coherent A G'C circuit 5 to the component detector 6.
A digital multiplication/addition circuit (multiplier,
A digital circuit that combines an adder and a latch circuit) performs phase detection, integrates the sampling number determined by the above PSK subcarrier frequency/bit rate ratio, and calculates the integer (2) of the PSK sampling clock from the numerically controlled oscillator 14. N squared) timing clock (
This is done by dumping using dump clocks a and b). The DA converter 18 performs DA conversion on the engineering signal component of the dumped output and outputs it as a PCM signal which is a PSK demodulated video signal.

The dumped I and Q signal components are input to a demodulation error detector 8 and an AGC calculation/lock determination unit 17. The phase error component detected by the I and Q signal components in the demodulation error detector 8 is output to the loop filter 12, and the loop filter 12 calculates and outputs a control signal for the numerically controlled oscillator 14.

The AGC calculation/lock determination unit 17 calculates the I and Q signal components, and sends the AGC signal to the coherent AGC circuit 5.
The lock status is output for controlling the operation mode of the loop filter 12, and the lock status is also output to the outside for display.

The loop filter 12 digitally performs processing equivalent to a conventional analog loop filter, averages the output of the demodulation error detector 8, and then outputs the output from the numerically controlled oscillator 14.
The phase error data of the subcarrier frequency is output.

The numerically controlled oscillators 14 and 15 are circuits corresponding to voltage controlled oscillator circuits (VCO) of conventional analog circuits, and are based on the clock from the clock generation synthesizer l and perform PSK.
A loop filter 12 or 1 is applied to sampling frequency data corresponding to the subcarrier frequency or bit rate.
The phase error data processed in step 3 is added to the data integrated by the digital multiplier/adder circuit, and the frequency component of the PSK subcarrier or bit rate sampling clock from the clock generation synthesizer 1 can be digitally changed. be.

The sampling clock from the numerically controlled oscillator 14 is S
SIN with IN waveform generator 10 and CO8 waveform generator 11
generate parallel data corresponding to waves and CO8 waves,
■Component detector6. It is output to the Q component detector 7 and the bit synchronization error detector 9.

The dump clock C of the demodulation error detector 8 is also generated by the numerically controlled oscillator 14 as a timing clock of 1/integer (2 to the N3 power) of the subcarrier sampling clock frequency.

In parallel with the above PSK demodulation operation, the digital multiplication and addition circuit of the bit synchronization error detector 9 performs coherent AGC once.
SIN to PCM-PSK sampling data from 15
The mid-bit of the signal data detected by multiplying the wave data is integrated and dumped at a timing that is an integer (2 to the power of N4) of the bit rate from the timing generator 16. The phase difference is output to the loop filter 13 as phase error information.

The loop filter 13 calculates and outputs control amount data for the numerically controlled oscillator 15 based on the phase error information from the bit synchronization error detector 9. The sampling frequency of the numerically controlled oscillator 15 is changed according to the control amount data so that bit synchronization can be achieved. The timing generator 16 is
It generates a dump clock d for the bit synchronization error detector 9 based on the output of the numerically controlled oscillator 15, and also outputs the synchronization clock to the outside.

As explained above, the embodiment shown in FIG.
Bit synchronization is also achieved at the same time as SK detection.

〔Effect of the invention〕

As explained above, the present invention eliminates the need for complex demodulation synchronization loop adjustment and downsizes by configuring the main parts of the PSK demodulation circuit and bit synchronization circuit, which are conventional analog circuits, with digital circuits. , the performance can be improved, and bit synchronization can be achieved at the same time as PSK demodulation of the PCM-PSK baseband signal, which has the effect of shortening the time required for demodulation operation.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Synthesizer for clock generation, 2... Low-pass filter, 3... AGC circuit, 4... A-D converter,
5... Coherent AGC circuit, 6... I component detector, 7... Q component detector, 8... Demodulation error detector,
9...Bit synchronization error detector, 10...SIN waveform generator, ]1...CoS waveform generator, 12.13...
・Loop filter, 14.15... numerically controlled oscillator,
16... Timing generator, 17... AGC calculation/tough 2 judger 8... D-A converter.

Claims (3)

[Claims] (1) An A-D converter that digitizes a two-phase PSK signal, a Costas-type demodulation loop that digitally demodulates the phase of the digital signal output from this A-D converter, and an A-D converter that is installed in parallel with this demodulation loop. and a bit synchronized loop for digitally extracting a synchronized clock from the digital signal outputted from the A-D converter. (2) The device according to claim 1, further comprising an automatic gain control circuit that controls the level of the digital signal output by the A-D converter based on the demodulated data component obtained by the demodulation loop.
SK demodulation method. (3) The bit synchronized loop includes a numerically controlled oscillator that outputs the synchronized clock by being phase-controlled by a control signal, and a numerically controlled oscillator that outputs the synchronized clock by controlling the phase of the digital signal outputted by the A-D converter. 3. A multiplication and addition circuit for phase error detection that performs synchronous detection at the timing of the center bit of said two-phase PSK signal based on the above, and a digital loop filter that generates said control signal from an output signal of said multiplication and addition circuit. PSK demodulation method described.