JPH04100109A - Redundant synchronous control method for programmable controllers - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 1] The present invention relates to a dual synchronous control system for a programmable controller I/roller that executes a plurality of processes using interrupts.

[Prior Art] Control systems that require high system reliability often have a duplex configuration in which two control devices with the same configuration are connected in parallel. Generally, in the case of a programmable controller having such a duplex configuration, the input section and the output section are common, and only the arithmetic section is duplexed. That is, data input manually from a common input section is processed in parallel in the duplicated computing sections, and then the computed results are output to the common output section. Even if one of the duplicated calculation units fails, the system will not stop because the other healthy calculation unit continues processing.

In such a programmable controller, in order to prevent the control process from being adversely affected in the event of a failure in one of the processing units, a redundant synchronous control method is required to simultaneously execute the processing of the dual processing units. Become. As the first system of this type of duplex synchronous control system, JP-A No. 5!
As seen in '172506, an address comparator and an address launch circuit are provided to compare the execution addresses of the microprocessors of both systems, and hold the one with the larger execution address as the one in progress. on the other hand,
There is a method of synchronously controlling both systems by regarding the one with the smaller execution address as being delayed and continuing the processing.

In addition, as a second method, Japanese Patent Application Laid-Open No. 62-187901
As seen in the publication, there is a method in which the arithmetic units of both systems are provided with endless counters that count each time a series of sequence control calculations are completed, and the two systems are synchronously controlled by comparing the count values. be.

[Problems to be Solved by the Invention] In such a programmable controller, the operations of both systems do not always need to be synchronized. In other words, synchronization is required only for input/output processing and interrupt processing for the common input/output unit, and for other processing, even if there is a slight synchronization difference, it will not have a negative impact on the control process. do not have.

However, in the conventional technology as described above, synchronous control is performed even in situations where it is not necessary, and therefore the control load caused by hardware or software becomes a problem.

That is, in the first method, one of the microprocessors
Special hardware is required to synchronize each instruction, and if a modern microprocessor that executes one instruction per clock is used, as the operating clock frequency increases, hardware synchronization control becomes necessary. There is a problem that the circuit cannot follow the operation of the microprocessor.

In addition, in the second method, synchronization control is performed by software every time a series of sequence control calculations is completed, so there is a problem that as the number of sequence control calculations increases, the software overhead for synchronization control also increases. .

This invention was made to solve the above-mentioned problems by providing special hardware to synchronize each microprocessor instruction by performing duplex synchronization control only when necessary. It is an object of the present invention to provide a duplex synchronous control method for a programmable controller that can reduce software overhead time for duplex synchronous control.

[Means for Solving the Problems] In order to achieve the above object, the present invention takes the following measures. That is, in a programmable controller with a duplex configuration in which two arithmetic units having the same function are connected in parallel to a common input part and a common output part, the two arithmetic units need to execute in synchronization. A match signal is generated by comparing a synchronization level number, which is a number unique to a certain first process and is output in response to the start of the first process, with a synchronization level number output from the two calculation units. or a synchronization level comparator that returns a mismatch signal, and if the match signal is returned, the first process is started, and if the match signal is returned, the first process is not started and the first process is restarted. The synchronization level number is output to the synchronization level comparator to perform dual system same month control.

[Operation] In other words, in the processing of the duplicated arithmetic units, different synchronization level numbers are provided for only those processes that require duplex synchronization to identify the processes and to set the priority of the processes. Here, by allowing a high-priority process to interrupt a low-priority process and transmit a synchronization level number, duplex synchronization control can be performed by synchronizing the start timing of processes in both systems.

[Example〕 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, in which a programmable controller 1 includes an input section 2, duplex calculation sections 3a and 3b, an output section 4, and a synchronous level comparator 5.

FIG. 2 is a flowchart showing the processing in the calculation section 3a3b in the embodiment of the present invention.

This processing is carried out by the calculation units 3a, 3b? This requires redundant synchronization control such as interrupt processing, has a unique synchronization level number, and executes the next step.

The NC synchronization level number is sent to the synchronization level comparator 5.

, (Step 1) (2) Wait for a response signal from the synchronization level comparator 5.

If there is a response signal, proceed to step 3. (Step (3)
The response signal from the synchronization level comparator 5 is determined. If the response signals do not match, the process returns to step 1, and if -i, the process proceeds to step 4. (Step 3) (4) Execute the calculation. (Step 4) FIG. 3 is a flowchart showing the processing in the synchronization level comparator 5 in the embodiment of the present invention.

This process performs the following steps.

(1) Wait until the synchronization level number sent from the calculation units 3a and 3b is received. Once received from both systems, proceed to step 2 (Step 1) (2) Compare the synchronization level numbers received from both systems. If the synchronization level numbers match, the process proceeds to step 3; if they do not match, the process proceeds to step 4. (Step 2) (3) Arithmetic unit 3a
, 3b.

(Step 3) (4) Return a mismatch signal to the calculation units 3a and 3b.

(Step 4) In this way, for processes that require redundant synchronization, synchronization control is performed at the time of starting the process, so no synchronization deviation that would adversely affect the control B process occurs.

[Effect of the invention 1] As described above, according to the present invention, there is no need to synchronize the dual systems for each instruction of the microprocessor.
It is possible to perform duplex synchronization control without being affected by the architecture or execution speed of the microprocessor. Further, by performing the synchronization process only when necessary, it is possible to reduce the software override time required for the synchronization process, which has the effect of preventing a decrease in control performance due to duplication.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a flowchart showing processing in the calculation units 3a and 3b, and FIG. 3 is a flowchart showing processing in the synchronization level comparator. ]...Programmable controller 2...Input section, 3a, 3b...Calculation section 4...Output section, 5...Synchronous level comparator Figure 1 Patent applicant Yaskawa Electric Manufacturing Co., Ltd.

Claims (1)

[Claims] In a programmable controller equipped with a duplex configuration in which two arithmetic units having the same function are connected in parallel to a common input part and a common output part, the two arithmetic units need to be executed in synchronization. The synchronization level number, which is a number unique to one process and is output in response to the start of the first process, is compared with the synchronization level number output from the two calculation units, and a match signal or a mismatch is detected. and a synchronization level comparator that returns a signal, and if the coincidence signal is returned, the first processing is started, and if the mismatch signal is returned, the synchronization level is changed again without starting the first processing. A dual synchronous control method for a programmable controller, characterized in that a number is output to the synchronous level comparator to perform dual system synchronous control.