JPH04100174A - Automatic generation device for circuit diagram - Google Patents

Automatic generation device for circuit diagram

Info

Publication number
JPH04100174A
JPH04100174A JP2217669A JP21766990A JPH04100174A JP H04100174 A JPH04100174 A JP H04100174A JP 2217669 A JP2217669 A JP 2217669A JP 21766990 A JP21766990 A JP 21766990A JP H04100174 A JPH04100174 A JP H04100174A
Authority
JP
Japan
Prior art keywords
wiring
circuit diagram
connection information
signal
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2217669A
Other languages
Japanese (ja)
Other versions
JP2682214B2 (en
Inventor
Naotaka Maeda
直孝 前田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2217669A priority Critical patent/JP2682214B2/en
Publication of JPH04100174A publication Critical patent/JPH04100174A/en
Application granted granted Critical
Publication of JP2682214B2 publication Critical patent/JP2682214B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To automatically generate a circuit diagram which is close to a manually generated circuit diagram and easy to see by recognizing signals which need not be wired on the circuit diagram and not regarding those signals as objects to be wired, but displaying the present of them clearly instead. CONSTITUTION:A unwired signal recognizing means 2 calculates the numbers of branches of respective signals by a branch quantity calculating means 21 and extracts candidates for unwired signals. An unwired signal determining means 22 determines the unwired signals in consideration of pin attributes of elements at branch destinations and an unwired signal registering means 23 registers them in internal data structure. Then an unwired signal elucidating means 5 selects one of the unwired signals recognized by the unwired signal recognizing means 2 and a branch destination selecting means 32 selects one of the elements at the branch destinations. Consequently, the circuit diagram which is automatically generated can be made easy to see.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、回路の接続情報から回路図を生成する回路図
自動生成装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an automatic circuit diagram generation device that generates a circuit diagram from circuit connection information.

〔概要〕〔overview〕

本発明は、自動生成された回路図の表示手段において、 クロック信号などの明確な信号の配線を省略してするこ
とにより、 配線図を見やすくすることができるようにしたものであ
る。
The present invention is a means for displaying automatically generated circuit diagrams that makes the wiring diagram easier to see by omitting wiring for clear signals such as clock signals.

〔従来の技術〕[Conventional technology]

従来、この種の回路図自動生成装置は、素子を配置した
後にすべての素子間の配線を行っていた。
Conventionally, this type of automatic circuit diagram generation apparatus has wired all the elements after arranging the elements.

〔発明が解決しようとする課題] このように従来例ではすべての配線を行うので、クロッ
ク信号等の多数の素子に分岐していて、かつ意味の明確
な信号で、通常の人手作成の回路図では配線が省略され
るような信号も配線の対象になり、自動生成された回路
図がかえって見にくくなったり、対象になる配線数が増
加し、このために自動生成時の処理時間が増加または配
線できない場合が出る欠点がある。
[Problems to be Solved by the Invention] In this way, in the conventional example, all the wiring is done, so the circuit diagram is divided into many elements such as clock signals, and the signals have clear meanings. In this case, signals for which wiring would be omitted are also subject to wiring, which may make the automatically generated circuit diagram difficult to read or increase the number of subject lines, which increases the processing time during automatic generation or increases the number of wiring lines. There is a drawback that it may not be possible.

本発明は、このような欠点を除去するもので、回路図上
で配線する必要のない信号を認識し、これらの信号は配
線対象とはせずに、代わりにその存在を明示する回路図
自動生成装置を提供することを目的とする。
The present invention eliminates these shortcomings by creating an automatic circuit diagram that recognizes signals that do not need to be routed on a circuit diagram, does not route these signals, and instead indicates their presence. The purpose is to provide a generation device.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は、素子を含む回路図を表示する表示手段と、素
子を含む回路図の接続情報を入力し、内部データに変換
して格納する接続情報入力手段と、この内部データに基
づき素子の配置座標を決定する配置情報を生成する配置
手段と、素子間の配線経路を決定する配線情報を生成す
る配線手段と、上記配置手段が生成した配置情報および
上記配線手段が生成した配線情報を上記表示手段に与え
る配置および配線結果出力手段とを備えたに回路図自動
生成装置において、上記接続情報入力手段が入力した接
続情報から上記表示手段に表示する必要のない配線にか
かわる接続情報を認識する非配線信号認識手段と、この
非配線信号認識手段で認識した接続情報の存在を示すデ
ータを上記表示手段に表示する非配線信号明示手段とを
備えたことを特徴とする。
The present invention provides a display means for displaying a circuit diagram including an element, a connection information input means for inputting connection information of the circuit diagram including the element, converting it into internal data and storing it, and arranging the element based on the internal data. a placement unit that generates placement information for determining coordinates; a wiring unit that generates wiring information that determines wiring routes between elements; and displaying the placement information generated by the placement unit and the wiring information generated by the wiring unit. In the automatic circuit diagram generation device, the automatic circuit diagram generation device is equipped with a layout given to the device and a wiring result output device, which recognizes connection information related to wiring that does not need to be displayed on the display device from the connection information input by the connection information input device. The present invention is characterized by comprising a wiring signal recognition means and a non-wire signal display means for displaying data indicating the existence of the connection information recognized by the non-wire signal recognition means on the display means.

また、上記非配線信号認識手段に代わり、上記表示手段
に表示する必要のない配線にかかわる接続情報が与えら
れる外部指定入力手段およびこの外部指定入力手段が入
力した接続情報を内部データに変換して格納する非配線
信号登録手段を備え、上記非配線信号明示手段は、この
非配線信号登録手段が格納する接続情報の存在を示すデ
ータを上記表示手段に表示する構成であっても良い。
In addition, in place of the non-wire signal recognition means, an external specified input means is provided with connection information related to wiring that does not need to be displayed on the display means, and the connection information input by this external specified input means is converted into internal data. The non-wire signal registering means may include a non-wire signal registering means for storing, and the non-wire signal clarifying means may display on the display means data indicating the existence of the connection information stored by the non-wire signal registering means.

〔作用〕[Effect]

クロック信号などのように、多数の素子に分岐していて
、かつ、意味の明瞭な信号の通過する配線は、人手作成
の回路図では省略される。本発明は、このような場合に
、信号名やシンボルを素子の接続点付近に示して配線の
表示をやめ、見やすい表示にする。
Wiring, such as a clock signal, which branches to a large number of elements and through which a signal with a clear meaning passes, is omitted in a manually created circuit diagram. In such a case, the present invention displays signal names and symbols near the connection points of elements, eliminates the display of wiring, and makes the display easier to see.

〔実施例〕〔Example〕

以下、本発明の実施例について図面を参照して説明する
Embodiments of the present invention will be described below with reference to the drawings.

第1図は本発明実施例の構成を示す全体構成図である。FIG. 1 is an overall configuration diagram showing the configuration of an embodiment of the present invention.

この実施例は、第1図に示すように、接続情報入力手段
1、非配線信号認識手段2、配置手段3、配線手段4、
非配線信号明示手段5および配置および配線結果主手段
6から構成される。
In this embodiment, as shown in FIG. 1, connection information input means 1, non-wired signal recognition means 2, arrangement means 3, wiring means 4,
It is composed of a non-wiring signal clarifying means 5 and a placement and wiring result main means 6.

ここで、非配線信号認識手段2は、第2図に示すように
、分岐数計算手段21、非配線信号決定手段22および
非配線信号登録手段23から構成され、また、非配線信
号明示手段5は、第3図に示すように、非配線信号選択
手段31、分岐先選択手段32、シンボル配置手段33
、分岐先終了判定手段34および非配線信号選択終了判
定手段35から構成される。
Here, as shown in FIG. 2, the non-wired signal recognition means 2 includes a branch number calculation means 21, a non-wired signal determination means 22, and a non-wired signal registration means 23, and also includes a non-wired signal clarifying means 5. As shown in FIG.
, a branch destination end determining means 34, and a non-wiring signal selection end determining means 35.

すなわち、この第一実施例は、第1図ないし第3図に示
すように、素子を含む回路図を表示する表示手段(図外
)と、素子を含む回路図の接続情報を入力し、内部デー
タに変換して格納する接続情報入力手段1と、この内部
データに基づき素子の配置座標を決定する配置情報を生
成する配置手段3と、素子間の配線経路を決定する配線
情報を生成する配線手段4と、配置手段3が生成した配
置情報および配線手段4が生成した配線情報を上記表示
手段に与える配置および配線結果出力手段6とを備え、
さらに、本発明の特徴とする手段として、接続情報入力
手段1が入力した接続情報から上記表示手段に表示する
必要のない配線にかかわる接続情報を認識する非配線信
号認識手段2と、この非配線信号認識手段2で認識した
接続情報の存在を示すデータを上記表示手段に表示する
非配線信号明示手段5とを備える。
That is, in this first embodiment, as shown in FIGS. 1 to 3, a display means (not shown) for displaying a circuit diagram including an element, connection information of the circuit diagram including the element is input, and the internal Connection information input means 1 that converts into data and stores it, placement means 3 that generates placement information that determines the placement coordinates of elements based on this internal data, and wiring that generates wiring information that determines wiring routes between elements. means 4, and placement and wiring result output means 6 for providing the placement information generated by the placement device 3 and the wiring information generated by the wiring device 4 to the display device,
Furthermore, as a feature of the present invention, the non-wiring signal recognition means 2 recognizes connection information related to wiring that does not need to be displayed on the display means from the connection information input by the connection information input means 1, and A non-wire signal indicating means 5 is provided for displaying data indicating the existence of the connection information recognized by the signal recognition means 2 on the display means.

すなわち、別の実施例は、非配線信号認識手段2に代わ
り、−上記表示手段に表示する必要のない配線にかかわ
る接続情報が与えられる外部指定入力手段61およびこ
の外部指定入力手段が入力した接続情報を内部データに
変換して格納する非配線信号登録手段62を備え、非配
線信号明示手段5は、この非配線信号登録手段62が格
納する接続情報の存在を示すデータを上記表示手段に表
示する構成である。
That is, in another embodiment, instead of the non-wire signal recognition means 2, - an external specification input means 61 to which connection information related to wiring that does not need to be displayed on the display means is given, and a connection input by this external specification input means; The non-wire signal registration means 62 converts information into internal data and stores it, and the non-wire signal display means 5 displays data indicating the existence of the connection information stored by the non-wire signal registration means 62 on the display means. The configuration is as follows.

次に、この実施例の動作について図面を参照して説明す
る。
Next, the operation of this embodiment will be explained with reference to the drawings.

回路の接続情報が入力されると、接続情報入力手段1は
これを内部データ構造に変換して格納する。次に、非配
線信号認識手段2は、分岐数計算手段21により各信号
の分岐数を計算し、非配線信号の候補を抽出する。非配
線信号決定手段22は、これを基に分岐先の素子のピン
属性等も考慮に入れて非配線信号を決定し、非配線信号
登録手段23はこれを内部データ構造に登録する。次に
、配置手段3はすべての素子の配置座標を決定し、配線
手段4は非配線信号認識手段2により非配線信号とJ 
IJ!されたもの以外のすべての信号の配線経路を決定
する。非配線信号明示す段5は、非配線信号選択手段3
1により非配線信号認識手段2で認識された非配線信号
の一つを選択し、分岐先選択手段32はこの信号の分岐
先の素子を一つ選択する。
When circuit connection information is input, the connection information input means 1 converts it into an internal data structure and stores it. Next, the non-wire signal recognition means 2 calculates the number of branches of each signal using the branch number calculation means 21, and extracts candidates for non-wire signals. The non-wire signal determining means 22 determines a non-wire signal based on this, taking into consideration the pin attributes of the branch destination element, and the non-wire signal registering means 23 registers this in the internal data structure. Next, the placement means 3 determines the placement coordinates of all the elements, and the wiring means 4 uses the non-wire signal recognition means 2 to identify the non-wire signal and J
IJ! Determine the wiring routes for all signals other than those specified. The stage 5 for specifying non-wired signals is the non-wired signal selection means 3.
1, one of the non-wire signals recognized by the non-wire signal recognition means 2 is selected, and the branch destination selection means 32 selects one element as the branch destination of this signal.

第4図はこうして選択された素子の一例で、素子c41
、信号S42、S43はすでに配置、配線されている。
FIG. 4 shows an example of elements selected in this way, with element c41
, signals S42 and S43 have already been placed and wired.

シンボル配置手段33は、これに対して非配線信号を明
示するシンボルsym44および信号名S45を配置す
る。次に、分岐先終了判定手段34によりずべての分岐
先処理を終了したかの判定を行い、終了していなければ
分岐先選択手段32からの処理を繰り返す。すべての分
岐先の処理が終了した場合には、非配線信号選択終了判
定手段35により他に未処理の非配線信号が存在するか
どうか判定を行い、あれば非配線信号選択手段31から
の処理を繰り返す。最後に配置および配線結果出力手段
6が第5図に例示したような結果を出力して処理を終了
する。
The symbol placement means 33 places a symbol sym44 and a signal name S45 that clearly indicate a non-wired signal on this signal. Next, the branch destination end determination means 34 determines whether all branch destination processing has been completed, and if not, the processing from the branch destination selection means 32 is repeated. When the processing of all branch destinations is completed, the non-wired signal selection completion determination means 35 determines whether there are any other unprocessed non-wired signals, and if so, the processing from the non-wired signal selection means 31 is performed. repeat. Finally, the placement and wiring result output means 6 outputs the results as illustrated in FIG. 5, and the process ends.

第6図は実施例の非配線信号認識手段2を別な手段で実
現した実施例の構成図であり、外部指定入力手段61お
よび非配線信号登録手段62から構成される。この実施
例では、非配線信号は外部指定入力手段61により外部
から取り込まれ、非配線信号登録手段62はこれを内部
データ構造に登録する。
FIG. 6 is a block diagram of an embodiment in which the non-wired signal recognition means 2 of the embodiment is realized by another means, and is composed of external designation input means 61 and non-wired signal registration means 62. In this embodiment, the non-wire signal is taken in from the outside by the external designation input means 61, and the non-wire signal registration means 62 registers it in the internal data structure.

〔発明の効果〕〔Effect of the invention〕

本発明は、以上説明したように、回路図上で配線する必
要のない信号を認識し、これらの信号を配線対象とはせ
ずに、代わりにその存在を明示することにより、自動生
成された回路図をより人手作成の回路図に近い、見やす
いものとすることができ、また、自動生成時の処理時間
を短縮したり、配線できない信号数を減らすことができ
る効果がある。
As explained above, the present invention recognizes signals that do not need to be wired on a circuit diagram, and does not include these signals as wiring targets, but instead clearly indicates their existence. It is possible to make the circuit diagram more similar to a manually created circuit diagram and to make it easier to see, and also has the effect of shortening the processing time during automatic generation and reducing the number of signals that cannot be wired.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明実施例の全体構成図。 第2図は第1図の非配線信号認識手段2の構成を示す図
。 第3図は第1図の非配線信号明示手段5の構成を示す図
。 第4図は第3図の分岐先選択手段32により選択された
素子の一例を示す図。 第5図は本方式により生成された回路図の一例を示す図
。 第6図は第1図の非配線信号認識手段2を別な手段で実
現した別の実施例の構成を示す図。 1・・・接続情報入力手段、2・・・非配線信号認識手
段、3・・・配置手段、4・・・配線手段、5・・・非
配線信号明示手段、6・・・配置および配線結果出力手
段、21・・・分岐数計算手段、22・・・非配線信号
決定手段、23・・・非配線信号登録手段、31・・・
非配線信号選択手段、32・・・分岐先選択手段、33
・・・シンボル配置手段、34・・・分岐先終了判定手
段、35・・・非配線信号選択終了判定手段、61・・
・外部指定入力手段、62・・・非配線信号登録手段。
FIG. 1 is an overall configuration diagram of an embodiment of the present invention. FIG. 2 is a diagram showing the configuration of the non-wired signal recognition means 2 of FIG. 1. FIG. 3 is a diagram showing the configuration of the non-wire signal clarifying means 5 of FIG. 1. FIG. 4 is a diagram showing an example of elements selected by the branch destination selection means 32 of FIG. 3. FIG. 5 is a diagram showing an example of a circuit diagram generated by this method. FIG. 6 is a diagram showing the configuration of another embodiment in which the non-wired signal recognition means 2 of FIG. 1 is realized by a different means. DESCRIPTION OF SYMBOLS 1... Connection information input means, 2... Non-wiring signal recognition means, 3... Arranging means, 4... Wiring means, 5... Non-wiring signal clarifying means, 6... Placement and wiring Result output means, 21... Branch number calculation means, 22... Non-wire signal determining means, 23... Non-wire signal registration means, 31...
Non-wired signal selection means, 32...branch destination selection means, 33
. . . Symbol arrangement means, 34 . . . Branch destination end determination means, 35 . . . Non-wired signal selection end determination means, 61 .
- External specification input means, 62... non-wired signal registration means.

Claims (1)

【特許請求の範囲】 1、素子を含む回路図を表示する表示手段と、素子を含
む回路図の接続情報を入力し、内部データに変換して格
納する接続情報入力手段と、この内部データに基づき素
子の配置座標を決定する配置情報を生成する配置手段と
、 素子間の配線経路を決定する配線情報を生成する配線手
段と、 上記配置手段が生成した配置情報および上記配線手段が
生成した配線情報を上記表示手段に与える配置および配
線結果出力手段と を備えたに回路図自動生成装置において、 上記接続情報入力手段が入力した接続情報から上記表示
手段に表示する必要のない配線にかかわる接続情報を認
識する非配線信号認識手段と、この非配線信号認識手段
で認識した接続情報の存在を示すデータを上記表示手段
に表示する非配線信号明示手段と を備えたことを特徴とする回路図自動生成装置。 2、上記非配線信号認識手段に代わり、上記表示手段に
表示する必要のない配線にかかわる接続情報が与えられ
る外部指定入力手段およびこの外部指定入力手段が入力
した接続情報を内部データに変換して格納する非配線信
号登録手段を備え、上記非配線信号明示手段は、この非
配線信号登録手段が格納する接続情報の存在を示すデー
タを上記表示手段に表示する構成である 特許請求項1記載の回路図自動生成装置。
[Claims] 1. A display means for displaying a circuit diagram including an element, a connection information input means for inputting connection information of the circuit diagram including an element, converting it into internal data and storing it, a placement unit that generates placement information that determines placement coordinates of elements based on the arrangement; a wiring unit that generates wiring information that determines wiring routes between elements; and placement information generated by the placement unit and wiring generated by the wiring unit. In an automatic circuit diagram generation device comprising a layout and wiring result output means for supplying information to the display means, connection information related to wiring that does not need to be displayed on the display means is obtained from connection information input by the connection information input means. and a non-wire signal display means for displaying data indicating the existence of connection information recognized by the non-wire signal recognition means on the display means. generator. 2. In place of the non-wiring signal recognition means, an external specified input means is provided with connection information related to wiring that does not need to be displayed on the display means, and the connection information input by this external specified input means is converted into internal data. 2. The method according to claim 1, further comprising a non-wire signal registering means for storing the non-wire signal, and the non-wire signal clarifying means is configured to display data indicating the existence of the connection information stored by the non-wire signal register on the display means. Automatic circuit diagram generation device.
JP2217669A 1990-08-17 1990-08-17 Automatic circuit diagram generator Expired - Fee Related JP2682214B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2217669A JP2682214B2 (en) 1990-08-17 1990-08-17 Automatic circuit diagram generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2217669A JP2682214B2 (en) 1990-08-17 1990-08-17 Automatic circuit diagram generator

Publications (2)

Publication Number Publication Date
JPH04100174A true JPH04100174A (en) 1992-04-02
JP2682214B2 JP2682214B2 (en) 1997-11-26

Family

ID=16707867

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2217669A Expired - Fee Related JP2682214B2 (en) 1990-08-17 1990-08-17 Automatic circuit diagram generator

Country Status (1)

Country Link
JP (1) JP2682214B2 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62272367A (en) * 1986-05-21 1987-11-26 Nec Corp Logic circuit diagram having multibit expression structure
JPS63100575A (en) * 1986-10-17 1988-05-02 Toshiba Corp Emphasizing and displaying system for sub line for logic circuit diagram
JPS63146163A (en) * 1986-12-09 1988-06-18 Nec Corp Generating system for logic circuit diagram

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62272367A (en) * 1986-05-21 1987-11-26 Nec Corp Logic circuit diagram having multibit expression structure
JPS63100575A (en) * 1986-10-17 1988-05-02 Toshiba Corp Emphasizing and displaying system for sub line for logic circuit diagram
JPS63146163A (en) * 1986-12-09 1988-06-18 Nec Corp Generating system for logic circuit diagram

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