JPH0410033A - microprocessor with redundant registers - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a microprocessor, and more particularly to a macroprocessor having redundant registers for improving yield. [Conventional technology]

As a conventional register cell, for example, Calm Mead,
Written by Lynn Conway: Introduction to LVSI Systems, page 163 (Carver M
ead and Lynn Contzay: I
ntroducti. n to VLSI Systems, pp, 1
63) shows a cell of a two-vote register. When expressed using an inverter, it is expressed as shown in FIG. Hereinafter, this will be referred to as a type I register cell. type l
In the register cell, inverter 1.2 and transistor 3 form a closed circuit to hold data. φ2 is one of the two-phase non-overlapping clocks φ□ and φ2. Signals LdA, LdB, RdA, and RdB are signals that are turned on during the period of clock φ□. When inputting register data from bus BA, Ld
The A signal becomes high level, transistor 4 is turned on, transistor 3 is turned off, and the data of BA is transmitted to inverter 1.2. When inputting data from bus BB to register, LdB
The signal is at a high level, transistor 5 is turned on, transistor 3 is turned off, and the value of BB is transmitted to inverters 1 and 2. It is prohibited to make the LdA signal and the LdB signal high level at the same time. In order to output the value of the register to BA, it is sufficient to set the RdA signal to a high level and turn on the transistor 6. In order to output the value of the register to BB, it is sufficient to set the RdB signal to a high level and turn on the transistor 7. The RdA signal and the RdB signal may be set to high level at the same time. Type I register cells are CM OS (Complete
Mentary Metal Oxide Sem1c
(onductor) circuit consisting of nine transistors.

[Problem to be solved by the invention]

When configuring a register file using the register cells shown in Figure 2, unless the register file has redundancy, there is a problem that if there is a failure in even one place, the register file will not operate as expected. was there. SUMMARY OF THE INVENTION An object of the present invention is to provide a microprocessor having redundant registers that can avoid a failure even if a failure occurs in a part of the register file.

[Means to solve the problem]

In order to achieve the above purpose, n in the microprocessor
Provide one or more spare registers for each register,
A configuration including means for storing whether or not a failure exists in the n registers, and a switching mechanism for accessing a spare register when the n registers are accessed according to the storing means. do.

[Operation] When a failure is discovered in some of the n registers. Switch access to the failed register to access to the spare register. This makes it possible to avoid manufacturing defects that occur in the register. [Example] Hereinafter, a first example of the present invention will be described using the drawings. FIG. 1 is a diagram showing an embodiment of the present invention. The microprocessor 501 includes an input/output control unit 502, an instruction decoder 503, a control circuit 504, a register control circuit 505, an address register (ADH) 506, a data register (DTR) 507, and a program counter (PC).
) 508, arithmetic logic unit (ALU) 509, defect relief information storage circuits 160 to 163, register file 51
Consists of 0. Register file 51.0 is
This is a register with redundancy. For example, register RO
In addition to 1R1, R2, and R3, it has a spare register Rs. ADR, DTR, PC, ALU, and register file are connected to bus BA511 and bus BB512, respectively. Microprocessor 501 executes normal instructions as follows. The value of PC is transferred to ADH via bus BA or BB. Under the control of the input/output control unit,
The value of ADH is output outside the chip through address pin 520. At this time, a command is input to the DTR from an external memory (not shown) at the address through the data bin 521. The command input to the DTR is decoded by the command decoder 503 and sent to the ALU through the control circuit 504.
509 etc. A register file 510 is controlled through a control circuit 504 and a register control circuit 505. When an extension is required to execute instructions, the PC
The value of 508 is updated, the updated address is output from the address pin, and the contents of the updated address are sent to DTR.
is loaded into. 504 is composed of a microprogram ROM or a random circuit. An example of testing register RO using processor instructions will be shown. The test of the register RO is performed by writing all O's and checking that the read data is all O's, and further writing all 1's and checking that the read data is all 1's. For example, when (1) MOV O/lzo, RO is executed, all O's are written to register RO. Next, consider the case where (2) MOV RO, address O is executed. If there is no failure in the chip, the address pins will be all O's and the data pins will be all O's. In other cases, it can be determined that a failure has occurred somewhere in the chip. In particular, if the databin values are not all O,
It is determined that there is a failure in the DTR 507, buses BA, BB, register RO, etc. Similarly, (3) MOV all 1. RO (4) When executing MOV Ro, address 0, if there is no failure in the chip, the address pins will be all O's and the data bins will be all 1's. In other cases, it can be determined that a failure has occurred somewhere in the chip. In particular, if the databin values are not all 1, DTR5
07, it is determined that there is a failure in buses BA, BB, register RO, etc. Furthermore, a similar program is executed for register R1. That is, (1') MOV all ○, R1 (2') M
Execute OV R1, O address and check whether the address pins are all O and the data bins are all O. Furthermore, (3') MO
V all 1. R1(4') MOV R1,○
Execute the address and check whether the address pins are all O's and the data bins are all 1's. Instructions (1') to (2') are executed as expected. When instructions (1) to (2) result in an operation that differs from the expected value, it can be determined that a failure has occurred in the register RO. Using the above method, by observing the data bin of the chip while executing instructions, register RO-R3
The presence or absence of a failure can be determined. As a result of the test, if a failure occurs only in register R○,
Writing is performed in the defect relief information storage circuit 160,
The defect relief information storage circuit 160 outputs a high level. Similarly, the test result register R1,
If a failure is found only in R2 and R3, writing is performed in the respective defect relief information storage circuits 161, 162, and 163, and a high level is output from each. If a failure occurs in any one of the registers RO to R3, the failure can be relieved by writing to the defect relief information storage circuits 160 to 163. Register RO, R1,
If there is a failure in two or more of R2 and R3, it is impossible to repair the failure in the embodiment shown in FIG. One method for writing into the defect relief information storage circuit is to cut the fuse on the chip using a laser. FIG. 3 shows an example of a circuit that can be written to after the chip is manufactured. FIG. 3 is composed of a laser-cuttable fuse 300, a transistor 301, a resistor 302, and a transistor 303. Hughes 30
0 is in a connected state at the time of manufacture. At this time, the gate of the transistor 303 becomes high level, and the gate of the transistor 303 becomes high level.
03 is turned on. As a result, the potential of the node 304 becomes low level, and the output 305 becomes low level. On the other hand, consider a case where the fuse 300 is cut by a laser. Charge is injected into node 304 through resistor 303 . At this time, the transistor 301 is turned on, and the source of the transistor 301 becomes low level. As a result, transistor 303 is turned off. Output 305 becomes high level. Another method for writing to the defect relief information storage circuit is as follows. That is, as shown in Figure 4,
The chip has a test mode pin 522, a high voltage pin 523,
External pins 524,525,526 are provided. When the test mode pin 522 is at a high level and a high voltage (for example, 10V) is applied to the high voltage pin 523, the external pin 524
~527 directly to the defect relief information storage circuits 170-1.
Defect relief information is written in 73. FIG. 5 shows an example of a defect relief information circuit when electrical writing is performed from an external pin. Test mode pin 52
2 to high level, high voltage to high voltage pin 523 (for example, 1
0v) is applied and each of the external pins 524 to 527 is set to a high level, transistors 306 and 307 are turned on, and a high voltage is applied to the fuse 300, causing it to blow. That is, it has been written into the defect relief information storage circuits 170-173. Test mode settings. It is not limited to test mote pins. The defect relief information storage circuit does not necessarily have to be a fuse; for example, a nonvolatile element may be used. The register testing method described above is a method using a processor program. In addition, test programs can also be stored in the chip's memory. For example, (1”) MOV All o, RO (2”) CMP All O, RO (3”) B
NZ ROFLT (4”) MOV All 1. RO (5”) CM P All 1. RO (6')
Execute BNZ ROFLT to determine whether register RO may contain a fault. Instruction (1'') writes all 0s to register RO. Instruction (2'') compares register RO and all 0s. In instruction (3"), if the comparison result is non-zero, branch to the instruction labeled with ROFLT. If the comparison result is zero, execute the next succeeding instruction. In instruction (4"), all 1s are executed. is written to register RO. In instruction (5"), register RO is compared with all 1s. In instruction (6"), when the comparison result is non-zero, RO is
Branch to the instruction labeled with FLT. When the comparison result is zero, execute the next succeeding instruction. Consider the following program as a program labeled with ROFLT. (7”) ROFLT:MOV All O, R1 (
8") CMP All O, R1 (9") BNZ FAULT (10' MOV All 1.R1 (11") CM
P All 1. R1 (12”) BNZ FAULT The above program is integrated on the chip,
There is also a method to execute it at power-on reset. In this case, the defect relief information storage circuit may be a normal flip-flop and no fuse is required. In FIG. 6, defect relief information storage circuits 180 to 1 are connected to bus BA.
An example in which 83 is connected is shown. In this case, it can be set, for example, by a transfer command that can be executed only in test mode. FIG. 7 is an example of the configuration of a register file according to the present invention. In FIG. 7, registers 140, 141, 142,
In addition to 143, a register 144 is provided. These registers are designated as registers RO1R1 and R2, respectively.
, R3, and R5. Register R3 is a spare register. If a failure occurs in any one of registers RO, R1, R2, or R3, register R is replaced with the failed register.
8 is used. Each register has the same configuration as the register shown in FIG. i.e. 4 type register cells 50.51.52
．． It consists of 53. The circuit in Figure 7 is composed of 20 type register cells, so 9X20=1
It consists of 80 transistors. FIG. 8 shows a decoding circuit that controls the register file of FIG. 7. 4 identical decoding circuits '10.11
1.112.113. This will be called a type 1 decoding circuit. The input to the decoding circuit 110 is LdA SE LO
11 signal, LdA ST B signal, clock φ□, defect relief information storage circuit 160.161.162.1
This is the output of 63. Defect relief information storage circuits 160 to 16
3 is a circuit that can be written to after the integrated circuit is manufactured. In the embodiment shown in FIG. 8, a low level is output during manufacturing. There is a failure in the register RO, and the defect relief information storage circuit 1
A case where writing is performed in 60 will be explained. If both the LdA S E L O11 signal becomes low level and both LdA ST B and clock φ become high level, the LdAR8 signal becomes high level. The LdARO signal remains at low level. That is, writing is performed to register R8 instead of register RO. Registers R1, R2,
If R3 is selected and the LdSTB signal and clock φ2 are at high level, LdARl, LdAR2, and Ld
The AR3 signal becomes high level, but the LdAR8 signal does not become high level. Similarly, defect relief information storage circuit 161.162.163
If writing occurs in registers R1 and R, respectively,
2. Register R5 is accessed instead of R3. A truth table of decoding circuit 110 is shown in FIG. The type 1 decoding circuit is a CMOS circuit composed of 86 transistors. The configurations of decode circuits 111, 112, and 113 are the same as that of decode circuit 110. The decoding circuit 111 includes the defect relief information storage circuit 160.
When a write occurs to 161.162.163, the write to registers RO, R1, R2, and R3 from bus BB is changed to register R8, respectively. The decoding circuit 112 includes the defect relief information storage circuit 160.
When a write occurs to 161, 162, and 163, the read from registers RO, R1, R2, and R3 to bus BA is changed to register R3. The decode circuit 113 includes the defect relief information storage circuit 160.
When a write occurs to 161.162.163, the read from registers RO, R1, R2, and R3 to bus BB is changed to register R8. As mentioned above, the register files shown in FIGS.
Even if one of the registers fails, it is possible to switch to the spare register R3 and operate it. The register files in Figures 7 and 8 are 180+8
Consists of 6×4=524 h transistors. For comparison, an example of the configuration of a register file without redundancy will be explained using drawings. That is, FIG. 9 shows an example of a register file using the type register cell shown in FIG. 2 and having a configuration of 4 bits×4. In FIG. 9, 1o, 11, 12, and 13 each represent a decoding circuit, 40 represents a register RO141, a register R1, 42 a register R2, and 43 a register R3. Register RO is type register cell 5o, 51.52
．． It consists of 53. type register cell 50
．． 51, 52, and 53 are the 0-3rd bits (BAo-BA3) of bus BA and the 0-3rd bits (BAo-BA3) of bus B, respectively.
B Bo-B B,). Decode circuits 11, 12, and 13 are the same circuits as decode circuit 1o. Below, decoding circuit 10.11.12
．． 13 will be called a type 2 decoding circuit. The type 2 decoding circuit is a CMOS circuit composed of 44 transistors. The decode code circuit 10 is a circuit that controls data writing from the bus BA (BA.-BA,) to the registers RO, R1, R2, and R3. The LdA S E L O signal, L
The dASELI signal, the LdA ST B signal, and the clock φ are input, and the signal line 20.21.22.23
is output. The truth table is shown in FIG. LdA S E L O1111 times, 4 registers R
Select one from O, R1, R2, R3 (7). Ld
If the AST B signal is at a high level, it indicates that there is a register into which data is written from bus BA. L
When the dA S T B signal is low level, LdASE
Regardless of the LO11 signal, signal lines 20.21.22.
23 are all at low level. The decode circuit 11 is a circuit that controls writing from the bus BB (BBo-BB3) to the registers RO, R1, R2, and R3. This is the same logic circuit as the decoding circuit 10. The decoding circuit 12 includes registers RO, R1, R2, and R3.
This circuit controls reading from the bus BA (BAo-BA3). This is the same logic circuit as the decode circuit 10. The decoding circuit 13 includes registers RO, R1, R2, and R3.
This circuit controls reading from the bus BB (BBo-BB,). This is the same logic circuit as the decode circuit 10. The type 2 register cell is composed of nine transistors, and the registers RO, R1, R2, and R3 are each composed of four cells. Therefore, register RO1R1 in FIG.
, R2, and R3 are composed of a total of 9×16=144 transistors. Further, each type 2 decoder circuit is composed of 44 transistors, and in FIG. 9, four type 1 decoders are used. Therefore, the decoding circuit 10.1 shown in FIG.
1.12.13 is composed of 4×44=176 transistors. Therefore, the circuit shown in FIG. 9 is composed of a total of 320 transistors. The register file shown in FIGS. 7 and 8 is comprised of 180+86X4=524 transistors, as described above. Compared to the circuit in Figure 9, the number of transistors is 5.
An overhead of 24/320=1.64 occurs. Next, another embodiment of the present invention will be described. FIG. 10 is an example of a register cell (hereinafter referred to as a type 2 register cell) having two closed circuits for data storage. The difference from the type 1 cell shown in FIG.
2', transistors 3', 6', and 7' were added. In Fig. 10, the first cycle is the second cycle.
It is formed by an inverter 1.2 and a transistor 3 as shown in the figure. Writing from the buses BA and BB and reading data to the buses BA and BB are the same as in the cell of FIG. 2. The second closed circuit is formed by inverters 1', 2' and transistor 3'. Write operations from buses BA and BB and data read operations to buses BB and BA are performed in the first
It is similar to the cycle of That is, by setting the LdA signal to high level, writing from bus BA is performed, and by setting the LdB signal to high level, writing is performed from bus B.
Writing is performed from B. By setting the RdAS signal to a high level, data is read to the bus BA, and by setting the RdBS signal to a high level, data is read to the bus BB. The number of transistors in a type 2 register cell is 16 in a CMO3 circuit.
It is individual. FIG. 11 shows an example of the configuration of a register file using type 2 register cells. 240 is register RO1241
represents register R1, 242 represents register R2, and 243 represents register R3. The configuration of each register is the same. Register RO is a type 2 register cell 50'51',
It consists of 52' and 53'. The type 2 register cells 50', 51', 52', and 53' are connected to the 0-3rd bits (BA-BA,) of the bus BA and the 0-3rd bits (BB-BB3) of the bus Bf7, respectively. There is. FIG. 12 shows a control circuit for the register file shown in FIG. 11. This control circuit is a type 2 decoder 21
0.211. It consists of type 3 decoders 212, 213 and a field writable circuit 164. The input and output signals of type 2 decoders 210 and 211 are similar to those of type 2 decoding circuit 10 shown in FIG. 9, and their operation follows the truth table shown in FIG. 16. The input signal of the type 3 decoding circuit 212 is RdASEL
O signal, RdA S E L 1 signal, RdA S T
These are the B-time signal clock φ□ and the output from the field write enable circuit 164. The output signals of the type 3 decoding circuit are the RclA RO signal, the RdARO3 signal,
RdAR1 signal, RdARIS signal, RdAR2 signal,
RdA R2S signal, RdAR3 signal, RdA R3S
signal, RdBRO signal, RdBROS signal, RdBR1
signal, RdBRIS signal, RdBR2 signal, RdB R
2S signal, RdBR3 signal, and RdB R3S signal. The truth table of the type 3 decoding circuit is shown in FIG. FIG. 13 shows an example of a type 3 decoding circuit that implements the truth table of FIG. 17. The circuit shown in FIG. 13 is a CMO5 circuit composed of 78 transistors. FIG. 14 shows an example of a microprocessor having the registers shown in FIGS. 10-13. The differences from the embodiment shown in Figure 1.4.6 are (1) type 2 register cell (
(2) one defect relief information storage circuit 190 is used. The register file 510' can be tested using microprocessor instructions, as in the first embodiment. Alternatively, it is also possible to incorporate a test program inside the chip. As a result of the test, if there is no failure in the registers RO1R1, R2, and R3, no writing is performed in the defect relief information storage circuit 190, and a low level is output. As a result of the test, if a failure occurs in one or more of the registers RO, R1, R2, R3, the defect relief information storage circuit 190
writing is performed. In the embodiment shown in FIG. 14, when a high level is applied to the test mode pin 522 and a high voltage (for example, 10) is applied to the high voltage pin 523, writing is performed in the defect relief information storage circuit 190. As a result, the second circuit of the type 2 register cell is used. The number of transistors in the register file 510' and register control circuit 505' in FIG. 14, excluding the defect relief information storage circuit, is as follows. That is, since there are 16 type 2 register cells, two type 2 decoder circuits, and two type 3 decoder circuits, there are 16×16+2×44+2×78=500 transistors. Compared to the register file in Figure 9, the number of transistors is 50.
0/320=1.56 times the overhead. In the embodiment of the present invention, an example is shown in which there are four 4-bit registers. However, the bit length and number of registers are not limited to these. Also, the first
In the embodiment described above, the number of redundant registers is one, but it is also possible to provide two or more redundant registers. As described above, according to the present invention, even if a failure occurs in a part of an integrated circuit, the failure can be avoided, which is effective in improving the yield of integrated circuits.

[Brief explanation of drawings]

1, 4, 6, and 14 are circuit block diagrams of a microprocessor according to an embodiment of the present invention, FIG. 2 is a circuit diagram of a conventional register cell (type 1), and FIG. FIG. 5 is a circuit diagram of an embodiment of a defect relief information storage circuit, FIGS. 7 and 11 are circuit block diagrams of an embodiment of a register file having redundant registers, and FIG. 8 is a circuit diagram of an embodiment of a register file having redundant registers. FIG. 9 is a circuit block diagram showing an example of a control circuit. FIG. 9 is a circuit block diagram showing an example of a non-redundant register file and its control circuit. FIG. 10 is a (type 2) register cell according to an embodiment of the present invention. 12 is a circuit block diagram showing an embodiment of the control circuit of the ledge staff file in FIG. 11, and FIG. 13 is a type 3 embodiment of the present invention.
15, 16, and 17 are diagrams showing truth tables of the decoding circuit.

Claims (1)

[Claims] 1. A microprocessor having at least an arithmetic unit, a plurality of buses, means for outputting address signals, and means for inputting and outputting data, comprising n registers for storing data, and one A microcontroller comprising the above redundant register, means for storing which register has a fault, and means for switching the selection signal of the n registers to the redundant register selection signal according to the value of the means for storing the fault register. processor. 2. The microprocessor according to claim 1, which detects register failure using microprocessor instructions. 3. The microprocessor according to claim 1, which detects a failure in a register by a program stored inside the microprocessor and writes the detected failure into a means for storing the failure register. 4. A microprocessor having at least an arithmetic unit, a plurality of buses, a means for outputting address signals, and a means for inputting and outputting data, including n registers for storing data, and a microprocessor for each of the n registers. A redundant register is provided, and means for storing whether a failure exists in the n registers that store the data is provided, and a selection signal for the n registers is set as the redundant register selection signal in accordance with a value of the storage means. A microprocessor having means for switching. 5. The microprocessor according to claim 4, which detects register failure using microprocessor instructions. 6. The microprocessor according to claim 4, which detects a failure in a register by a program stored inside the microprocessor and writes the detected failure into a means for storing the failure register.