JPH0410036A - Monitor circuit for arithmetic processor - Google Patents

Abstract

PURPOSE:To increase the address space used by a user without deteriorating a monitoring function by deciding the presence or absence of abnormality of an arithmetic processor after deciding whether the signal production timing is fixed or not. CONSTITUTION:A detection means 121 detects the production of signals, and a deciding means 123 decides the presence or absence of the abnormality of an arithmetic processor by deciding whether the signal production timing is fixed or not in accordance with the detecting result of the means 121. Thus it is notices that the signal is outputted in the fixed timing to a peripheral device connected to the arithmetic processor from this processor. Then the production of this signal is detected and the signal production timing is monitored. So that the presence or absence of the abnormality can be decided for the arithmetic processor. Thus no store address of a control means is required for the assignment address and the monitor signal to be applied to the watchdog timer (deciding means) 123. Then this address space can be used for another processing purpose.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a monitoring circuit for monitoring the presence or absence of an abnormality in an arithmetic processing unit.

[Prior Art] Conventionally, a monitoring circuit called a watchdog timer is connected to an arithmetic processing device, for example, a microcomputer. The watchdog timer measures the generation cycle of a pulse signal that is output from the microcomputer to the watchdog timer at a fixed period. If this pulse signal is not generated after a fixed period of time, the microcomputer is abnormal. It is determined that this is the case and the microcomputer is stopped.

[Problems to be Solved by the Invention] However, in conventional devices of this kind, in order to output a signal for abnormality monitoring from the arithmetic processing unit to the watchdog timer, a specific address for the watchdog timer and a signal for abnormality monitoring are required. A memory address must be provided to store the control procedure for generating the signal. Moreover, once this specific address is set, the address cannot be changed, so there is no continuity between the address area before and the area after this address, and there are restrictions on the address assignment of the equipment to be used.

Therefore, the purpose of the present invention is to eliminate such problems,
An object of the present invention is to provide a monitoring circuit for an arithmetic processing device that can increase the address space used by a user without impairing conventional monitoring functions.

[Means for Solving the Problems] In order to achieve such an object, the present invention solves the problem of an abnormality in an arithmetic processing device that is connected to a peripheral device and supplies a signal to the peripheral device at a constant timing. A monitoring circuit for an arithmetic processing unit that monitors the presence or absence of the signal, comprising a detection means for detecting the generation of the signal, and whether or not the generation timing of the signal is at the constant timing according to the detection by the detection means. By determining whether there is an abnormality in the arithmetic processing device, it is determined whether or not there is an abnormality in the arithmetic processing device. The present invention is characterized by comprising a determination means. Further, the peripheral device of the present invention is a keyboard input device having a scanning type key matrix, and the generation of one specific signal among strobe signals supplied from the arithmetic processing unit for scanning the scanning type key matrix. The determining means is characterized in that the determining means determines the cycle or the interval between occurrences of two specific signals in the strobe signal.

[Function J] The present invention focuses on the fact that there is a signal output from the arithmetic processing device at a certain timing to peripheral equipment connected to the arithmetic processing device, detects the generation of this signal, and monitors the signal generation timing. By doing so, it is determined whether or not there is an abnormality in the arithmetic processing unit.

Furthermore, since the signal generation timing is monitored, for example, by monitoring the generation interval of two signals, the strobe signal to the key matrix of the keyboard input device can be used as a monitoring signal. Therefore, the generation cycle of the monitoring signal does not have to be a constant repeating cycle as in the conventional case, and it is also possible to use output signals of various output signals to peripheral devices as the monitoring signal.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows the circuit configuration of an embodiment of the present invention.

In FIG. 1, a microcomputer (CPU) 11
G, monitoring circuit 120, read-on memory (ROM) 13
0, a random access memory (RAM) 140 and a keyboard input device 150 are commonly connected to a data bus 61 and an address bus 62.

The CPU iio reads and executes an arithmetic program stored in the ROM 130 to perform predetermined processing, for example, arithmetic processing on information input from the keyboard input device 150. This calculation result is written into RAM 140.

The keyboard input device 150 has a scanning type key matrix 151 shown in FIG. Information BO~BX to CPU
A response is sent to 110.

The monitoring circuit 120 includes a decoder 121 and an AND gate 12.
2 and a watchdog timer 123.

Decoder 121 is connected to address bus 62, codes the address signal on address bus 62, and detects that the address signal is an address assigned to keyboard input device 150. During this time, the AND circuit 122
outputs a level-on signal for AND gate 1
Let's open 22.

The AND gate 122 is a specific 2-bit bit on the data bus 61. In this example, the keyboard input device 15
A bit for transferring the output scanning strobe signal AO1AX is input to 0, and this input bit signal is used as an output signal to the watchdog timer 123.

Therefore, the decoder 121 functions as a detection means, and the watchdog timer 123 functions as a determination means.

FIG. 2 shows a circuit configuration of a key matrix 151 used in the keyboard input device 150 of FIG. 1.

The key matrix 151 uses scanning pulse (strobe signal) signals AO to AX, which are sequentially generated in time series at the timing shown in FIG. do.

For example, when the key switch connecting the AO1BO signal line is pressed, B
A pulse signal BO is generated on the O signal line.

The CPU 110 identifies the position of the pressed key switch based on the “H” level and generation timing of the response signals BO to BX in response to the strobe signals AO to AX, identifies the position of the key switch, and presses the key switch. Perform predetermined information processing on the information.

In this embodiment, attention is paid to the fact that a strobe signal is outputted from the CPU 110 to the key matrix 51 at regular intervals in order to read input information from the keyboard input device 150.
Used for the monitoring signal in step 3.

Next, the circuit configuration of the watchdog timer 123 of this embodiment is shown in FIG.

The watchdog timer 123 of this embodiment monitors the time from the generation of strobe signal AO to the generation of AX and the time from strobe signal AX-AO.

For this purpose, a first counter 210 that monitors the interval between AO and AX and a second counter 220 that monitors the interval between AX and AO are provided. Both counters are initialized by a clear signal CLR generated when the power is turned on. When the strobe signal AO is input, the first counter 210 is activated, and when the strobe signal AX is input, the first counter 220 is cleared. During this time, the second counter 220 continues to be in a stopped state. Next, by inputting the strobe signal AX, the first
The counter 210 is in a stopped state, and the second counter 2
22 starts booting. The second counter stops operating upon input of the strobe signal AO. When either the strobe signal AO1AX is not generated due to an abnormality in the CPU 110, the first counter 210 or the second counter 220
is not clocked and at the end of time measurement, a signal WDT for resetting the CPU ILO is generated.

Next, another circuit configuration of the watchdog timer 123 is shown in FIG.

The watchdog timer of this example monitors the cycle of the strobe signal AO to the key matrix 51, and when multiple strobe signals AO occur within a certain period of time, or when no strobe signals occur (when no strobe signals occur), an abnormality detection signal or ,CPU
A reset signal WDT to 110 is generated.

In FIG. 5, the first monostable multi-by-break 310
When the strobe signal AO is input, it generates a pulse signal (see FIG. 6) for a fixed period T1 determined by a resistor R1 and a capacitor C1. Note that (TI for a certain period) <
(period of strobe signal AO) is determined in advance.

The second monostable multivibrator 320 is initialized by the initialization signal old at power-on, and then initialized (cleared) by the output pulse signal of the first monostable multivibrator 310. Further, after initialization, if it is not cleared midway, a pulse signal having a pulse width of 12 hours longer than T1 is generated.

When two or more strobe signals AO are generated during a certain period T, a reset signal WDT is created in the NAND circuit 303 using the output pulse signal of the first monostable multivibrator 310 and the second strobe signal AO. Ru. On the other hand, if the strobe signal AO is not generated even after a certain period T, the second monostable multi-by-break 3
12 hours after the 20th 8 Cal issue was cleared, it reversed,
This inverted signal becomes a reset signal piece.

As explained above, this book 1. In the second embodiment, the CPU
110 is a strobe signal A that is generated at a certain timing.
The normal operation of the CPU 110 is confirmed by monitoring the O1AX generation interval and the AO multiplication signal generation cycle. Therefore, the CPU 110 does not need to send a constant cycle signal to the watchdog timer 123. As a result, the address space previously allocated for the watchdog timer can be allocated for the user, and the control procedure for generating the watchdog timer clear signal is no longer required, and the memory storage area for this control procedure is also reduced. No longer needed.

In addition to this embodiment, the following examples are given.

1) In this embodiment, a keyboard input device is used as an example of a peripheral device. It is preferable to monitor the signal generation timing using a monitoring circuit.

[Effects of the Invention] As described above, according to the present invention, the address allocated to the watchdog timer and the storage address of the control means for outputting the monitoring signal can be made unnecessary, so that the address space thereof can be eliminated. can be used for its original purpose of arithmetic processing.

Furthermore, since the signal generation timing is monitored, for example, by monitoring the generation interval of two signals, the strobe signal to the key matrix of the keyboard input device can be used as a monitoring signal. For this reason, it is not necessary that the generation cycle of the monitoring signal be a constant repetition cycle as in the past (it is also possible to use output signals of various output signals to peripheral devices as the monitoring signal).

FIG.

...CPU, ...monitoring circuit, ···decoder, ...watchdog timer, ...Key matrix.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the circuit configuration of the embodiment of the present invention, FIG. 2 is a circuit diagram showing the circuit configuration of the key matrix 151 in FIG. 1, and FIG. 3 shows the strobe signal generation timing of the embodiment of the present invention. 4 is a block diagram showing the circuit configuration of the watchdog timer 123 shown in FIG. 1,

Claims (1)

[Scope of Claims] 1) A monitoring circuit for an arithmetic processing device that is connected to a peripheral device and that monitors the presence or absence of an abnormality in the arithmetic processing device that supplies signals to the peripheral device at a certain timing, a detection means for detecting the generation of the signal; and a detection means for determining whether or not the generation timing of the signal is at the constant timing according to the detection by the detection means, thereby determining whether or not there is an abnormality in the arithmetic processing device. 1. A monitoring circuit for an arithmetic processing device, comprising: determination means for making a determination. 2) The peripheral device is a keyboard input device having a scanning type key matrix, and the generation cycle of one specific signal among the strobe signals supplied from the arithmetic processing unit for scanning the scanning type key matrix or the corresponding 2. The monitoring circuit for an arithmetic processing device according to claim 1, wherein said determining means determines an interval between occurrences of two specific signals among strobe signals.