JPH04100403A - Binary transversal filter - Google Patents

Abstract

PURPOSE:To make the filter applicable to multilevel modulation without deteriorating its performance by constituting the filter so that the filter can select and send the output value of a set number of data sequences by using the 1st select signal from the outside to an adding means when the number of data sequences is set. CONSTITUTION:A waveform shaping sections 511 in a ROM 51 supplies an output value corresponding to the output of an SR 13 to an adder 514 through a 1/2-divider 513 and another waveform shaping section 512 supplies an output value corresponding to the output of another SR 12 to the adder 514 as it is and the addition output of the adder is supplied to the 1/2 dividing section 523 of a ROM 52. A waveform shaping section 522 in a ROM 52 supplies an output value corresponding to the output of an SR 11 to an adding section 524 as it is. Since the output of a 1/2-divider 523 is also supplied to the section 524, the addition output of the section 524 is sent to a D/A converter 41. The converter 41 converts the addition output into analog signals and sends the analog signals to a modulator (not shown in the figure) through a low-pass filter 42.

Description

[Detailed Description of the Invention] [Summary] For example, regarding a binary transversal filter used in a modulation section of a digital multiplexing radio device, 4 binary transversal filters for PSK modulation and applying the filter to multi-level QAM modulation. The purpose of this is to ensure that the performance does not deteriorate and the circuit scale does not increase.
a shift register means for writing the data of the series into the corresponding shift register portion using a clock faster than the data speed by a predetermined multiple, and outputting the data as parallel data;
- Consists of first to nth ROM parts storing output values corresponding to all possible states of parallel data output from the nth shift register part, corresponding to input parallel data. Send the output value. The output values of the ROM means and the first to nth ROM parts are set to 1 to (1/2°
-1) Adding means (3) that multiplies, adds, and sends out the added output, and digital/analog converting means (4) that converts the added output into an analog value, then limits the band and outputs it.
In the binary transversal filter having the above, the output values of the first to nth ROM portions are converted into a data series such that the maximum value of the addition output does not exceed the maximum value of the digital/analog conversion means. However, when the number of data series is set, the output value of the set number of series is selected using the first selection signal from the outside and sent to the adding means. Configure it so that
FIELD OF THE INVENTION The present invention relates to a binary transversal filter used, for example, in a modulation section of a digital multiplex radio device.

For example, in a modulation section of a digital multiplexing radio device, an input digital signal is band-limited using a binary transversal filter, and then a carrier wave is digitally modulated using the band-limited digital signal.

At this time, it is necessary to ensure that even if the binary transversal filter for 4PSK modulation is applied to multilevel QAM modulation, the performance will not deteriorate and the circuit scale will not become large.

[Prior art] Fig. 9 is a block diagram of a conventional example.
Binary transversal filter for K modulation, 9th
Figure (b) shows a binary transversal filter for 64-value QAM modulation, and Figure 1O is an explanatory diagram of the operation of Figure 9fa).

Hereinafter, the operation of Fig. 9 tal will be explained with reference to Fig. 10.
Either two series of data ah are input, or the circuit configuration is the same, so only the configuration of one series is shown.

First, input serial data is sequentially input into a 9, for example, 15-stage shift register (hereinafter abbreviated as SR) 11 using a sampling clock having a data rate of 4 times as shown in Figure 1O. Parallel data 1. ,
I2. . . 115 and added to the ROM 24.

The ROM 24 stores all (+a212+a313+") corresponding to all states of data I,, l,...115.
” Since the calculation result of +a+sI+5 is written, if only data I8 is 1 and other data is 0, the first
A waveform as shown in Figure 0-■ is output from the ROM 24. Also, when the data in ■ is continuous, the waveforms shown in Figure 10-■ are superimposed. Here, al+a2. a3...
・ is a predetermined coefficient.

Now, the output of the ROM 24 is converted into an analog signal by a digital/analog converter (hereinafter abbreviated as D/A converter) 64 of 9, for example, IO bits, and then converted into an analog signal by a low-pass filter 65 which converts the harmonics generated by the sampling clock. The wave components are removed and applied to a modulator (not shown).

Here, the maximum output value of RσM 24 is 10 bits of D/
Since it is adjusted to the maximum scale of the A converter, the points above and below the opening are +511. -512
, which increases the S/N ratio due to quantization noise (
It is for the purpose of Note that the solid line a is the waveform of "l".

The dotted line b indicates the "O" waveform.

In addition, Figure 1O-■ shows the low-pass filter 6 in Figure 9.
The eye pattern of the output of 5 is shown, a is the “l” waveform, b
is a waveform of “0”.

Next, FIG. 9(b) shows a circuit configuration when the binary transversal filter (hereinafter abbreviated as BTF) of FIG. 9 (al) is applied to 64-value QAM modulation.

As shown in the figure, since three series of data I1112+Is are input, 5RII-13 and ROMs 25-27 are provided corresponding to each series.

At this time, the output value of ROM 25 to ROM 27 is 2'(
a+L+ +atI+2n ” +also L's)
+2'(alL++a2IB ''' +alal
t+s)+2°(, alls+ + atlst ・
”+ a + s I□5) ・ Urn・(
It becomes 11.

Here, I+2 indicates the second data of the l series, the first term is the output of ROM +, the second term is the output of ROM2, and the third term is the output of ROM.
It takes the same form as modulation.

However, the output of the ROM is weighted as 2', 2', 2°, but in the case of 4 PSK modulation, the weighting is 20, so dividing each coefficient by 22 gives 4 PS.
A BTF configured for K modulation can be used.

That is, as shown in FIG. 9(b), the output of ROMz 25 is directly applied to the adder 63, but the output of ROMz 26.
The output of ROMa 27 is divided by 9% by dividers 61 and 62 and added to adder 63.

Then, the addition output added by the adder 63 is sent to the 10-bit D/A converter 64. The output is taken out through a low-pass filter 65.

[Problem to be solved by the invention]

Now, as shown in FIG. 11(a), which is an explanatory diagram of the problem, in the case of 4-phase PSK modulation, Ich or Qch receives l-series data, so only one ROM is used.
Even if a maximum output of 512 is sent from the ROM to the D/A converter, this converter will not overflow.

However, in the case of 16-value QAM modulation and 64-value QAM modulation, Ich or Qch has two or three sequences, so in either case, an adder is used and the D/A converter overflows.

Therefore, in order to prevent overflow, scaling is performed as shown in Fig. 11(b) to perform 16-value QAM modulation and 64-value QA modulation.
If the output value of M modulation is expressed as a percentage, it is approximately 2.5 dB for I66-value QA modulation and approximately 1.5 dB for 64-value QAM modulation.
There is a problem that a 2 dB S/N deterioration occurs.

There is also the problem that a divider and an adder are required, and the circuit scale becomes larger than in the case of 4PSK modulation.

[Means to solve problems]

1 to 3 show principle block diagrams of the first to third aspects of the present invention.

In the figure, ■ is composed of the first to nth shift length parts, and n series data is written to the corresponding shift register part using a clock that is faster than the data rate by a predetermined multiple, and is output as parallel data. The shift register means 2 comprises first to nth ROM parts storing output values corresponding to all possible states of the parallel data output from the first to nth shift register parts. It is a ROM means that outputs an output value corresponding to input parallel data.

In addition, 3 indicates the output values of the first to nth ROM portions from 1 to (
1/2'-1), and then adds the sum and sends out the added output. 4 is a digital/analog conversion means that converts the added output into an analog value, then limits the band and outputs it.

The output values of the first to nth ROM portions are scaled in accordance with the number of data series so that the maximum value of the addition output does not exceed the maximum value of the digital/analog converting means. However, when the number of data series is set,
The output values of the set number of sequences are selected using a first selection signal from the outside and sent to the adding means.

Further, in the second aspect of the present invention, the ROM means also includes the function of the addition means, so that the addition means provided outside is omitted.

Furthermore, the third aspect of the present invention writes the output values of the first to nth ROM portions in a plurality of types of codes, and adds a code conversion portion to the addition means.

The first to nth ROM parts send the output values of the codes corresponding to the second selection signals from the outside to the adding means, and the adding means converts the added outputs into digital/analog in the code converting part. It converts into a code that corresponds to the input conditions of the means and outputs it.

[Effect]

The first aspect of the present invention is to convert the output values of the first to n-th ROM portions into data series numbers such that the maximum value of the addition output is within the maximum value of the digital/analog conversion means and closest to the maximum value. Scale accordingly. Then, when the number n of data series is set, the output value of the set series is selected using the first selection signal from the outside and sent to the adding means.

This prevents the maximum scale of the digital/analog conversion means from being exceeded and the S/N from deteriorating.

The second aspect of the present invention is configured such that the first to n-th ROM portions also include the function of the addition means, thereby eliminating the addition means provided outside. As a result, the circuit scale in the case of multilevel QAM modulation becomes small, and the circuit scale becomes almost the same as in the case of 4PSK modulation.

In the third aspect of the present invention, the output values of the first to nth ROM portions are written in a plurality of types of codes, and a code conversion portion is added to the adding means.

Then, using a second selection signal from the outside, the output value written in the corresponding code is selected and sent to the adding means. The addition means simply executes division and addition using the selected coded output value, and then converts the addition output into a code corresponding to the input conditions of the digital/analog conversion means using the conversion section and outputs it. do.

〔Example〕

FIG. 4 is a block diagram of the first embodiment of the present invention, FIG. 5 is an explanatory diagram of the operation of FIG. 3, FIG. 6 is a block diagram of the second embodiment of the present invention, and FIG. 7 is a block diagram of the second embodiment of the present invention. FIG. 8 is a block diagram of the embodiment of FIG. 8, which is an explanatory diagram of division when two's complement representation is used.

Here, the shift registers 11 to 13 are constituent parts of the shifted/stuck means 1, the ROMs 21 to 23 are constituent parts of the ROM means 2, and the Sagi divider 32. V4 divider 31. Adder 33
are the constituent parts of the adding means 3, and the D/A converter 41. The low-pass filter 42 is a component of the digital/analog conversion means 4, and the ROM 51. The ROM 52 is a component of the ROM means 5, and the expansion calculator 71. Adder 72. Code converter 73 represents a component of addition means 7.

Note that the same reference numerals indicate the same objects throughout the figures. Hereinafter, n=3. The D/A converter is assumed to be 10 bits and will be explained with reference to FIG. 5, starting with the operation shown in FIG.

First, as shown in Fig. 5, the Ic
Since only one ROM is used when there is one h and Qch, the maximum output value of the ROM is set to 512.

However, in the case of the 16QAlt4 modulation method, there are two sequences and two ROMs are used, so scaling as shown in FIG. 5 is performed to make the maximum output value of the ROM 341.

At this time, the adder 33 contains 341 and R from the ROM 21.
Since 341 from OM 22 is applied to 170 by the 1/2 divider 32, it becomes 511, and the D/A converter does not overflow.

Similarly (in the case of 264 QAM modulation method, the maximum output value of ROM 21 is scaled to 292, and the added output is 51
Make it become 1. Note that a selection signal is applied to the ROM from the outside so that an output value corresponding to the modulation adjustment formula can be selected.

As a result, there is no S/N deterioration of the analog signal sent out from the low-pass filter 42 in each modulation method.

Next, FIG. 6 shows a ROM 5L 52 including division and addition functions. Here, the waveform shaping in the figure indicates that the above equation (1) is calculated.

That is, the waveform shaping section 511 in the ROM 51 is SR1.
The output value corresponding to the output of 3 is added to the adder 514 via the % divider 513. In addition, the waveform shaping portion 512 is SR
The output value corresponding to the output of 12 is directly added to the adder 514, and the added output is added to the % division section 523 of the ROM 52.

On the other hand, the waveform shaping section 522 in the ROM 52 is 5RI
The output value corresponding to the output of I is directly added to the addition section 524. Since the output of the % division section 523 is also added here, the sum is added and the added output is sent to the D/A converter 41. The D/A converter converts the signal into an analog signal, and then sends it to a modulator (not shown) via a low-pass filter 42.

This results in the same configuration as in FIG. 4, but since the divider by 9 and adder are provided in the ROM, the circuit scale does not become large.

As shown in the figure, a selection signal and a waveform shaping bypass signal are provided to enable support for a plurality of types of modulation methods and to enable external switching between use and non-use of the waveform shaping section.

Further, the operation shown in FIG. 7 will be explained with reference to FIG. Generally, D/A converters require straight binary data as shown in Figure 7(a), but in order to perform division, addition, etc.
This can be done more easily using the complement of . Note that FIG. 7(a) shows the 4PSK modulation method.

FIG. 7(b) shows the 16QAM modulation method.

For example, as shown on the left side of FIG. 8(b), when calculating each of 6 using two's complement, the first pit o is inserted into the second bit, and the second . 3rd bit. It can be inserted into the fourth bit.

Further, when calculating the percentage of -6 as shown on the right side of FIG. 8(b), the same process as above may be performed.

Furthermore, for example, when finding -4+1, use 1100 and 000.
When 1 is added, it becomes 1101, and -3 can be easily obtained. However, in the case of straight binary, -3 cannot be obtained by simple addition, and the operation becomes more complicated than when using two's complement.

Therefore, as shown in Fig. 7(a) and Fig. 7(b), the ROM
A code conversion section 73 is provided for writing the output values of 24 to 26 in straight binary and two's complement, and for converting the code from two's complement to straight binary.

Further, a required code output value is taken out from the ROM, and a code switching signal for controlling the operation of the code conversion section is externally applied.

Now, in the case of FIG. 7(a), since there is no division or addition, straight binary is selected as the code switching signal.

The output value of the ROM 24 is directly converted into an analog signal by a D/A converter 41, and a band-limited analog signal is outputted via a low-pass filter 42.

However, in Figure 7 (bl is divided because of the 16QAM modulation method.

Since addition is required, the two's complement output value is extracted from the ROM 25°26 using the code switching signal and the adder 72. y
Add to 2 divider 71. Therefore, this divider performs division as described above and adds it to the adder, which adds it to the output value from the ROM 25 and sends the added output to the code converter 73.

The code converter converts the code to straight binary and D
Since the signal is added to the /A converter 41, it is converted into an analog signal here and then sent to the outside via the low-pass filter 42.

That is, 4 PSK modulation binary transversal
Even if the filter is applied to multilevel QAM modulation, the performance will not deteriorate and the circuit scale will not increase.

〔Effect of the invention〕

As explained in detail above, according to the present invention, the binary transversal filter for 4PSK modulation is
Performance does not deteriorate even when applied for modulation.

Moreover, there is an effect that the circuit scale does not become large.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the first invention, and FIG. 2 is a block diagram of the principle of the second invention.
FIG. 3 is a block diagram of the principle of the third invention, FIG. 4 is a block diagram of the embodiment of the first invention, FIG. 5 is an explanatory diagram of the operation of FIG. 3, FIG. 6 is a block diagram of the second embodiment of the present invention, FIG. 7 is a block diagram of the third embodiment of the present invention, and FIG. 8 is an explanatory diagram of division when two's complement representation is used. FIG. 9 is a block diagram of a conventional example, FIG. 10 is an explanatory diagram of the operation of FIG. 9(a), and FIG. 11 is an explanatory diagram of problems and points. In the figure, l indicates shift register means 2, ROM means 3, and addition means 4, digital/analog conversion means. No. 1 map
δ diagram

Claims (1)

[Claims] 1. Consisting of first to nth (n is a positive integer) shift register parts, n series of data are handled using a clock that is faster than the data rate by a predetermined multiple. Shift register means (1) for writing in a shift register portion and outputting parallel data; and output values corresponding to all possible states of the parallel data output from the first to nth shift register portions are stored. ROM means (2) which outputs an output value corresponding to input parallel data; 1/2^n
^-^1) Adding means (3) that multiplies and then adds and sends out the added output, and after converting the added output into an analog value,
Digital/analog conversion means that outputs with limited bandwidth (
4) In the binary transversal filter having the following, the output values of the first to n-th ROM parts are data-transversal filters such that the maximum value of the addition output does not exceed the maximum value of the digital/analog conversion means. However, when the number of data series is set, the output value of the set number of series is selected using the first selection signal from the outside, and the adding means selects the output value of the set number of series. A binary transversal filter characterized in that it is configured to send out a signal. 2. The binary transversal filter according to claim 1, characterized in that the ROM means also includes the function of an addition means to eliminate the external addition means. . 3. In the binary transversal filter according to claim 1, the output values of the first to nth ROM parts are written in a plurality of types of codes, and a code conversion part is added to the addition means, The n-th ROM portion sends the output value of the code corresponding to the second selection signal from the outside to the adding means (7),
The binary transversal converter is characterized in that the addition means converts the addition output into a code corresponding to the input conditions of the digital/analog conversion means in the code conversion section and outputs the code to the digital/analog conversion means. filter.