JPH0410054A - Digital signal processor - Google Patents

Abstract

PURPOSE:To shorten the processing time for the approximate calculation by connecting the output of a multiplication means of a 2nd arithmetic part to one of both inputs of each of both multiplication means of the 1st and 2nd arithmetic parts. CONSTITUTION:The 1st and 2nd arithmetic parts include the digital multiplication means 13 and 18 which multiply the values of two digital signal data and the digital totalization means 14, 15, 19 and 20 which totalize the output values of both means 13 and 18. Then the output of the means 18 of the 2nd arithmetic part is connected to one of both inputs of each of both means 13 and 18 of the 1st and 2nd arithmetic parts respectively. Thus it is possible to decrease the number of program steps needed for transfer of the interim data carried out from the output of the totalization means during an operation. Then the processing time is shortened for the approximate calculation.

Description

DETAILED DESCRIPTION OF THE INVENTION BACKGROUND OF THE INVENTION The present invention relates to a digital signal processor (hereinafter referred to as DSP).

BACKGROUND ART An audio signal processing device capable of controlling a sound field in order to create reverberation and a sense of presence in an acoustic space such as a concert hall or a theater at home or in a car is known, for example, as disclosed in Japanese Patent Laid-Open No. 72615/1983. It is shown in the official gazette. Such an audio signal processing device performs sound field control by digitally processing an audio signal output from an audio signal source such as a tuner.
SP is provided. The DSP includes an arithmetic unit that performs arithmetic processing such as four arithmetic operations, a RAM that stores digital audio signal data to be supplied to the arithmetic unit, and digital coefficient signal data (hereinafter simply referred to as coefficient data) to be multiplied by the audio signal data. ) is stored as a coefficient RA
It is equipped with memory such as M. The DSP is configured to transfer signal data between each memory and from the memory to an arithmetic unit according to a predetermined program so that arithmetic processing of signal data can be repeatedly performed at high speed. Further, the program is written in a rewritable program memory such as RAM in the DSP, and the program is changed by a microcomputer outside the DSP each time the sound field mode is switched by operation. In other words, by changing the program, you can create any acoustic space.

A conventional DSP is provided with buffer memories 1 and 2, a multiplier 3, an ALU 4, and an accumulator 5, as shown in FIG. Further, a signal data RAM 6 for storing input digital signal data and a coefficient data RAM 7 for storing a plurality of coefficient data are provided. At the time of calculation, signal data is read from the signal data RAM 6 and supplied to the buffer memory 1 via the bus 8 and held therein, and coefficient data is sequentially read from the coefficient data RAM 7 at predetermined timing and sent to the buffer memory 2. is supplied and held. The value indicated by the data held in the buffer memory 1.2 is multiplied by the multiplier 3. The multiplication result by the multiplier 3 is added to the value held in the accumulator 5 by the ALU 4 and is held in the accumulator 5. This ALU 4 and accumulator 5 form an accumulation means. Further, the held output of the accumulator 5 is connected to the buffer memory 1 and the signal data RAM 6 via the bus 8, so that the held data is transferred.

In such a conventional DSP, there are cases where it is desired to perform nonlinear function calculations. This c41 is coefficient data, and X is signal data. However, the DSP shown in FIG.
In a configuration in which only coefficient data is supplied to the buffer memory 2 as shown in FIG. 2, it is impossible for the multiplier 3 to calculate the power of the signal data value X.

Furthermore, if the buffer memory 2 is connected to the bus 8 so that the signal data from the signal data RAM 6 is supplied to the buffer memory 1.2, and the multiplier 3 can calculate the power of the signal data value X, an approximate value can be obtained. I can do calculations.

However, the calculation result by the multiplier 3 is held in the accumulator and is also sent to the buffer memory 1 via the bus 8.
Or it is necessary to transfer to 2. For example, in order to calculate c2 After that, c2 and x2 are multiplied. Therefore,
New multiplications and accumulations cannot be performed until this data is transferred, resulting in a problem that the number of steps in the program increases and processing time increases.

Summary of the Invention [Object of the Invention] An object of the present invention is to provide a DSP that can reduce processing time in the case of approximate value calculation.

[Structure of the Invention] The DSP of the present invention comprises first and 'W' circuits each consisting of a digital multiplication means for multiplying the values of two digital signal data, and a digital accumulation means for accumulating the output value of the multiplication means.
&2 is a digital signal processor equipped with arithmetic units,
It is characterized in that the output of the multiplication means of the second calculation section is connected to one input of the multiplication means of both the first and second calculation sections.

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

In the DSP which is an embodiment of the present invention shown in FIG.
Two calculation units are provided. The first arithmetic unit includes buffer memories 11 and 12, a multiplier 13, an ALU 14, and an accumulator 15.

The outputs of the buffer memories 11, 12 are each connected to a multiplier 13. The output of the multiplier 13 is connected to one input of the ALU 14, and the output of the ALU 14 is connected to the accumulator 15. Accumulator 15 has two outputs, one output being connected to one input of ALU 14 and the other output being connected to bus 10 . Note that the buffer 7 memory 11 has two inputs, one input is connected to the coefficient data RAM 21 and the other input is connected to the bus 10. The buffer memory 12 has three inputs, the first of which is the signal data RAM 2.
2 and the second input is connected to bus 10.

Further, the second calculation section includes buffer memories 16 and 17, a multiplier 18, an ALU 19, and an accumulator 20,
It is configured similarly to the first arithmetic unit.

Also, one input of the buffer memory 16 is the coefficient data R.
AM23, and the other input is connected to bus 10. A first input of the buffer memory 17 is connected to the signal data RAM 24 and a second input is connected to the bus 10. However, the multiplier 18 of the second arithmetic unit has 3
The first output is connected to one input of the ALU 19, the second output is connected to the remaining third input of the buffer memory 12, and the third output is connected to the remaining third input of the buffer memory 17.
is connected to the third input of the .

Note that the coefficient data RAMs 21 and 24 are also connected to the bus 10. Further, the other input of the ALU 14 has two inputs, the first input is connected to the output of the multiplier 13,
A second input is connected to bus 10.

In addition, three inputs of the buffer memory 12, two inputs of the other buffer memories, three outputs of the multiplier 18,
Only one or two or more of the two outputs of the accumulators 15 and 20, the two outputs of the signal data RAM 22 and 24, and the other two inputs of the ALU 14 are made valid. These are configured, for example, by a switching circuit consisting of a plurality of three-state buffers and the like.

Reading operation of coefficient data from RAM21 and 23,
readout operation of signal data from RAMs 22 and 24;
Arithmetic operation of ALU14.19, accumulator 15.
Operations such as the output selection operation of the held data 20 and the output selection operation of the multiplier 18 are performed by the sequence controller (
(not shown). The sequence controller operates according to a program written in a program memory (not shown) within the DSP.

When calculating an approximate value of xn, coefficient data values CO+C1, C2, . . . , Cn are written into the coefficient data RAM 21 before the start of the calculation operation. Also, the audio signal data X supplied from the outside is stored in the signal data RAM.
22.

When an arithmetic operation is started, first, in a first step, signal data X is read out from the signal data RAM 24 and supplied to the buffer memories 12, 16 and 17.

On the other hand, coefficient data C1 is read out from the coefficient data RAM 21 and supplied to the buffer memory 11. Therefore,
The multiplier 13 multiplies the signal data X and the coefficient data a1.

The value CIX resulting from the multiplication by the multiplier 13 is supplied to the accumulator 15 via the ALU 14 and held in the second step, which is one step after the first step. Further, the - multiplier 18 multiplies the signal data X and performs square calculation. The value X2 resulting from the multiplication by the multiplier 18 is supplied to the buffer memories 12 and 17 in a second step.

In this second step, coefficient data c2 is read out from the coefficient data RAM 21 and supplied to the buffer memory 11. Therefore, the multiplier 13 uses x2 and the coefficient data value c
Multiply by 2. Value c2 of the multiplication result by the multiplier 13
x2 is supplied to the other first input of ALU 14. In synchronization with this supply, the data value CIX held in the accumulator 15 is supplied to one input of the ALU 14.

Therefore, in the third step, the ALU 14 calculates c1x+c
2x2 is accumulated, and the value of this accumulation result is held in the accumulator 15. Further, the multiplier 18 multiplies the signal data X held in the buffer memory 16 and the signal data x2 held in the buffer memory 17. The value X3 resulting from the multiplication by the multiplier 18 is supplied to the buffer memories 12 and 17 in a third step.

In the third step, coefficient data c3 is read out from the coefficient data RAM 21 and supplied to the buffer memory 11. Therefore, the multiplier 13 multiplies X3 by the coefficient data value c3. The value C3X' resulting from the multiplication by the multiplier 13 is supplied to the other first input of the ALU 14. In synchronization with this supply, the accumulated data value C1x+c2 x2 held in the accumulator 15 is supplied to one input of the ALU 14. Therefore, in the fourth step, ALU1
4 accumulates c1x + c2 x2 + c3 x',
The value of this accumulation result is held in the accumulator 15. Further, the multiplier 18 multiplies the signal data X held in the buffer memory 16 and the signal data x1 held in the buffer memory 17.

The value X resulting from the multiplication by the multiplier 18 is supplied to the buffer memories 12 and 17 in a fourth step.

is supplied to Accumulator 1 is synchronized with this supply.
The accumulated data value ΣCnxn held in ALU1
4. Therefore, ALU14 is c
o+Σcnxn is accumulated, and the value ΣC of this accumulation result is
fi xn is held in the accumulator 15. For example, in the case of n-4, as shown in FIG.
obtained by being retained in Note that the coefficient data from the coefficient data RAM 21 is C1, C2,...Cn+
It is read step by step in the order of C0.

In the above-described embodiment, ΣCnxn is calculated by repeating the above-described approximate value calculation operation. In the step after ΣCnxn is held in the accumulator 15, the coefficient data cm is read out from the coefficient data RAM 21 and inputted to the other second input of the accumulator, but the present invention can also be applied to other approximate value calculations. Can be applied.

Effects of the Invention As described above, in the DSP according to the present invention, the first and second channels each include a digital multiplication means for multiplying the values of two digital signal data, and a digital accumulation means for accumulating the output value of the multiplication means. An arithmetic unit is provided, and the output of the multiplication means of the second arithmetic unit is connected to one input of the multiplication means of both the first and second arithmetic units, respectively. Therefore, D.S.
Since it is not necessary to transfer intermediate result data from the output of the accumulating means to the multiplication means via the bus during the first calculation, the signal data and coefficient data can be read out from the memory at every step, resulting in efficient data processing. This makes it possible to reduce the number of program steps compared to the conventional method, thereby shortening the processing time.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the progress of approximate value calculation, and FIG. 3 is a diagram showing the configuration of a conventional DSP. Explanation of symbols of main parts 3.13. -18... Multiplier 4.14.19... ALU 5.15.20... Accumulator Figure 2 Figure 3

Claims (2)

[Claims] (1) A digital signal processor comprising first and second arithmetic units each consisting of a digital multiplier for multiplying the values of two digital signal data and a digital accumulator for accumulating the output value of the multiplier. , wherein an output of the multiplication means of the second arithmetic section is connected to one input of the multiplication means of both the first and second arithmetic sections, respectively. (2) The multiplication means of the second calculation section supplies data representing the multiplication result to the input of the accumulation means of the second calculation section and to one input of the multiplication means of both the first and second calculation sections. 2. A digital signal processor as claimed in claim 1.