JPH0410086A - Digital signal processor - Google Patents

Abstract

PURPOSE:To process the plural systems of data signals by the same program by providing a switching means to connect an output from any one of plural input ports to one input register selectively corresponding to a control signal. CONSTITUTION:A switching means 10 is provided to connect the output from any one of plural input ports IN1 and IN2 to one input register 6 selectively corresponding to the control signal. Therefore, the same processing as an arithmetic processing executed to the digital signals supplied to the first input port IN1 can be executed to the digital signal to be supplied to the second input port IN2 as well without changing the program written to the inside. Thus, since the number of programs to be stored in a memory in a microcomputer can be decreased, the memory having large memory capacity is not required and cost can be reduced.

Description

TECHNICAL FIELD The present invention relates to a digital signal processor (hereinafter referred to as DSP).

BACKGROUND ART An audio signal processing device capable of controlling a sound field in order to create reverberation and a sense of presence in an acoustic space such as a concert hall or a theater at home or in a car is known, for example, as disclosed in Japanese Patent Laid-Open No. 72615/1983. It is shown in the official gazette. Such an audio signal processing device performs sound field control by digitally processing an audio signal output from an audio signal source such as a tuner.
SP is provided. The DSP includes arithmetic means for performing arithmetic operations such as arithmetic operations, a data memory for storing audio signal data to be supplied to the arithmetic means, and a delay memory for delaying the signal data stored in the data memory. The DSP is configured to transfer signal data between each memory and from the memory to the calculation means according to a predetermined program so that calculation processing of the signal data can be repeatedly performed at high speed. Further, the program is written in a rewritable program memory such as RAM in the DSP, and the program is changed by a microcomputer outside the DSP each time the sound field mode is switched by operation.

In other words, by changing the program, you can create any acoustic space.

Further, some DSPs are equipped with a plurality of input ports for inputting digital signals. For example, as shown in FIG. 2, a signal obtained by digitizing an analog audio signal from an analog audio signal source 1 such as a tuner by an A/D converter 2 is supplied to the first port IN+ of the DSP 3, and the signal is digitized from a CD (compact disc). ) A digital audio signal from a digital audio signal source 4 such as a player is transmitted via a DIR (digital audio interface receiver) 5 to a second capo IN2 of the DSP 3.
is being supplied to. Input registers 6 and 7 are respectively provided in the first and second person cabs IN, , IN2, and the supplied digital audio signals are sequentially held in the input registers 6 and 7. Input registers 6, 7 are connected to a common data bus 8. This data bus 8
A data memory (not shown) of the arithmetic processing section 9 is connected to the DSP 3, and the digital signal data supplied to the DSP 3 is normally written into the data memory for arithmetic processing.

By the way, the signal data held in the input register 6 or 7 is transferred to an element such as a data memory according to a program written in the program memory. Therefore,
When input signal data held in the input register 6 is transferred to the data memory for arithmetic processing, and when input signal data held in the input register 7 is transferred to the data memory and then the same arithmetic processing is performed. A different program must be used, and the program must be transferred from the microcomputer and rewritten each time the input port for inputting the digital signal to be processed is switched. However, there is a problem in that a memory with a large storage capacity is required to store a large number of programs in a memory such as a ROM in a microcomputer for each input port.

Further, as shown in FIG. 3, as a conventional DSP, a changeover switch 10 is connected to the first and second person ports INI, IN2, and each input digital signal to the first and second person ports IN, IN2 is connected to a changeover switch 10. One of them is selectively supplied to the input register 6 by the changeover switch 10. Selection changeover of the changeover switch 10 is performed in response to commands from a microcomputer.

However, in this DSP, two systems of input ports, the first and second couplers IN, IN2, cannot be used at the same time. Therefore, one input port can usually handle only two channels of pig signals, so D
There is a problem in that it is not possible to connect SPs in cascade or to simultaneously input and process two systems (for four channels) of data signals.

Summary of the Invention [Object of the Invention] An object of the present invention is to be able to switch the input ports for inputting digital signals to be processed without having to store as many programs as the number of input ports in the memory of the microcomputer, and to operate a plurality of systems. It is an object of the present invention to provide a DSP capable of processing data signals of .

[Structure of the Invention] The DSP of the present invention has a plurality of input ports to which digital signals to be processed are supplied, and a data bus provided for each input port, which holds the digital signals supplied to the input ports and has a common output. D with an input register connected to
The SP is characterized by having a switching means for selectively connecting the output of any one of a plurality of input ports to one input register according to a control signal.

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

In the DSP which is an embodiment of the present invention shown in FIG. 1, a digital audio signal is supplied from the A/D converter 2 to the first port IN+, and the second input port IN
As before, the digital audio signal is supplied from the DIR5 to the DIR5. A changeover switch 10 as a switching means is connected to the first person port INI, and an input digital signal to the first person port IN+ is supplied to the input register 6 via the changeover switch 10. Further, the second input port IN2 is directly connected to the input register 7 and also connected to the changeover switch 10. The changeover switch 10 selectively relays and supplies a signal from either one of the first and second capos IN+ and 1N2 to the input register 6 in accordance with a control signal held in a control register 21, which will be described later.

The output of input register 6.7 is connected to data bus 8. The data bus 8 is connected via a buffer memory 19 to a data memory 11 that temporarily stores a data group and one input of a multiplier 12 . A coefficient memory 14 is connected to the other input of the multiplier 12 via a buffer memory 13, and a coefficient data group is stored in the coefficient memory 14.

One piece of coefficient data is sequentially read from a group of coefficient data stored in the coefficient memory 14 in response to a timing signal from a sequence controller 20, which will be described later, and is supplied to the buffer memory 13 and held therein. The coefficient data held in the buffer memory 13 is supplied to the multiplier 12. An ALU (adder) 15 is provided to accumulate the calculation output of the multiplier 12, and one input is supplied with the calculation output of the multiplier 15, and the other input is connected to the data bus 8. An accumulator 16 is connected to the calculation output of the ALU 15, and the output of the accumulator 16 is connected to the data bus 8. Further, output registers 17 and 18 are connected to the data bus 8. Output register 17
．． 18 holds the processed signal data and outputs the held data from the first and second output ports OUT+ and 0UT2.

Data memory 11, multiplier 12, coefficient memory 14, AL
The sequence controller 2 controls the operation timing of data transfer and calculations between elements such as U15 and accumulator 16.
Controlled by 0. The sequence controller 20 operates according to a processing program written in the program memory 30 and also operates according to instructions from the microcomputer 23. A control signal as a command from the microcomputer 23 is supplied to the above-mentioned control register 21 via the interface 22 and is held therein.

The microcomputer 23 controls rewriting of the processing program and rewriting of coefficient data in the coefficient memory 14 in response to key operations on the keyboard 24. The control register 21 has a plurality of holding bits each having a predetermined content to be held, and is used for synchronization between the input digital audio signal, the DSP 3 and the microcomputer 23, and the switch 10.
It is provided for exchanging information such as switching control.

Note that the DSP 3 is further provided with elements such as a memory control circuit that controls writing and reading of data in an externally connected memory in order to create delay data, and a delay time memory that stores a group of delay time data. It is not shown because it is not directly related to the present invention.

Further, DIR5 is provided to demodulate the digital signal subjected to biphase modulation.

In such a configuration, the selector switch 10 is normally in a state where the first person's cover IN is selected. This first
Person's capo IN, selected state is 1st person's capo) IN,
A digital audio signal from the A/D converter 2 is supplied as signal data to the input register 6 via the changeover switch 10. A program counter (not shown) operates from an initial value in synchronization with the signal data to the input register 6, and the operation steps of the program are sequentially read out from the program memory 30 and supplied to the sequence controller 30. Assuming that the program written in the program memory 30 is a first program that has an instruction step for transferring input signal data to the input register 6 to the data memory 11 and performs a predetermined arithmetic processing, the transfer instruction step In response to this, the sequence controller 30 generates an operation command signal, and the signal data held in the input register 6 is transferred to the data memory 11 via the data bus 8.
and written to a predetermined location.

As the predetermined calculation process, for example, the first person's cover IN
The input signal data of I is sequentially transferred and written into the data memory 11, and the signal data stored in the data memory 11 is sequentially read out and supplied to the buffer memory 19 to be held. On the other hand, coefficient data is sequentially read from the coefficient memory 14 and supplied to the buffer memory 13 where it is held. Coefficient data from the buffer memory 13 and signal data from one buffer memory are supplied to the multiplier 12, and the multiplier 12 multiplies them one after another. The value obtained by this multiplication is accumulated with the previous value (the value held in the accumulator 16) in the ALU 15, and the result of the calculation is held in the accumulator 16.

When the selector switch 10 is in the first input port IN+ selection state, the first input port IN+ is selected for the digital audio signal from the digital filter 5 supplied to the second input port IN2.
When performing the same arithmetic processing as the program, the program memory 30 has an instruction step for transferring the input signal data from the first program to the input register 7 to the data memory 11, as in the conventional case, and the predetermined arithmetic processing is performed. It is necessary to rewrite it to the second program.

However, when the selector switch 10 is in the first port IN+ selection state, for example, if a predetermined key on the keyboard 24 is operated and an input port switching command signal is generated, a new control signal is sent from the microcomputer 23 via the interface 22. It is supplied to a predetermined bit position of register 21 (connected to changeover switch 10).

Therefore, the content held at a predetermined bit position of the control register 21 is inverted from logic "0" to "1", for example. This causes the selector switch 10 to switch to the selection state of the second input port IN2. In the second input port IN2 selection state, the digital audio signal from DIR5 supplied to the second input port IN2 is input to the selector switch 1 as signal data.
0 to the input register 6. Therefore, in this case, the signal data supplied to the second input port IN2 is supplied to the input register 6 and held, so if a predetermined calculation process is performed, the signal data supplied to the second input port IN2 is the same as in the selected state. It is sufficient that the first program is stored in the block diagram memory 30. That is, the program counter operates from the initial value in synchronization with the signal data from the second input port IN2 to the input register 6, and the operation steps of the first program are sequentially read from the program memory 30 and supplied to the sequence controller 30. be done. The sequence controller 30 generates an operation command signal in response to the transfer command step of the first program, and the signal data held in the input register 6 is transferred to the data memory 11 via the data bus 8 and written to a predetermined location. be.

Note that the digital audio signal is a parallel data signal formed from a plurality of bits representing audio information, a clock bit, and left and right channel bits. The left and right channel bits indicate whether the audio information is in the left or right channel, for example, a logic “1” in the left channel.
, becomes logic "0" in the right channel. These left and right channel bits are supplied to the control register 21, and the above program counter is set to the left and right channel bits, for example.
The sequence controller 30 operates from the initial value in synchronization with the inversion from logic "0" to "1" and generates an operation command signal.

Further, in the embodiment described above, the changeover switch 10 selectively relays and supplies any one of the signals input to the first and second person ports INI and IN2 to the input register 6. Any one of the signals input to three or more input ports is input to one input register! ! You could even give them a bounty.

Effects of the Invention As described above, in the DSP of the present invention, the output of any one of the plurality of input ports is selectively set to 1 in accordance with the control signal.
Switching means is provided for connection to the input register of the input register.

Therefore, the same arithmetic processing performed on the digital signal supplied to the first input port is performed on the digital signal supplied to the second input port without changing the internally written program. be able to.

As a result, the number of programs to be stored in the memory in the microcomputer can be reduced, and a memory with a large storage capacity is not required, making it possible to reduce costs. Furthermore, since the number of times the program in the DSP is rewritten is reduced, there is also the advantage that the processing load on the microcomputer side is lightened.

It is also possible to simultaneously perform arithmetic processing on two digital signals supplied to the first and second input ports respectively.
You can use SPs in cascade connection, or use 4-channel A/
Two systems of output signals from the D converter can be simultaneously input and processed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIGS. 2 and 3 are block diagrams showing a conventional DSP. Explanation of symbols of main parts 3...DSP 6.7...Input register 10...Selector switch 21...Control register 23...Microcomputer

Claims (2)

[Claims] (1) A plurality of input ports to which digital signals to be processed are supplied, and an input register provided for each input port to hold the digital signals supplied to the input ports and whose output is connected to a common data bus. 1. A digital signal processor comprising: a switching means for selectively connecting an output of any one of the plurality of input ports to one input register according to a control signal. (2) The digital signal processor according to claim 1, further comprising a control register that holds a port switching command signal supplied from the outside as the control signal.