JPH04101436A - field effect transistor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a field effect transistor having a so-called pulse-doped structure.

[Prior art]

A field effect transistor having a pulse-doped structure has the advantage of suppressing the so-called short channel effect and having a small gate leakage current and capacitance.

As a field effect transistor with a conventional pulse-doped structure, “OMVPE grown GaAs MES
FETsvjth 5tep-doped channel
el ror MMICs” (198
Report of the GaAs ICC Symposium held in Nashville, Tennessee from November 6th to 9th, 2008, pp. 2
97-300) is known.

FIG. 3 is a sectional view showing the structure of the field effect transistor. This field effect transistor uses semi-insulating Ga
It has a pulse structure consisting of an undoped p-type GaAs layer 2 grown on an As substrate 1, a thin doped 0+ type GaAs layer 3, and an undoped n-type GaAs layer 4 with a lower impurity concentration.

[Problem to be solved by the invention]

However, compared to HEMTs that use a two-dimensional electron gas layer formed at the Peter junction interface as a channel layer, field effect transistors with a conventional pulsed topope structure have a lower carrier confinement effect and have lower mutual conductance. The FET characteristics were inferior.

Therefore, the present invention aims to improve FET characteristics such as mutual conductance in a field effect transistor having a pulse-doped structure.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a first conductivity type (for example, p
A second conductivity type (for example, n-type) channel layer is formed on this buffer layer, and an undoped second conductivity type (for example, n-type) channel layer doped with an impurity is formed on this channel layer. In a field effect transistor having a pulse-doped structure in which a conductivity type (e.g., n-type) cap layer is formed, a first conductivity type (e.g., p-type) having a higher impurity concentration than the buffer layer is provided between the buffer layer and the channel layer. A semiconductor layer is further interposed.

[Effect]

Since the present invention is constructed as described above, by inserting a crystal growth layer with a high impurity concentration, the gradient of the electric field at the pn junction becomes steeper, thereby increasing the carrier confinement effect.

〔Example〕

Hereinafter, a field effect transistor (
Hereinafter, the FET will be explained based on the attached drawings. In addition, in the description, the same reference numerals are used for the same elements, and redundant description will be omitted.

FIG. 1 shows an M using GaAs according to an embodiment of the present invention.
The configuration of ESFET is shown. The FET according to this example is
It is composed of a pulsed tope structure P formed on a semi-insulating GaAs substrate 1, and a source electrode S1, a drain electrode, and a gate electrode G formed on the surface thereof. An impurity implanted region into which n+ ions are implanted by self-alignment is formed below the source electrode S and drain electrode of the pulse-doped structure P.

This pulse structure P includes a buffer layer, a channel layer and a cap layer. In this example, an undoped p-type GaAs layer 2 is used as a buffer layer, an n+-type GaAs layer 3 is used as a channel layer, and an n+-type GaAs layer is used as a cap layer.
An n-type GaAs layer 4 having a lower impurity concentration than the s-layer 3 is used, and a p+-type GaAs layer 5 having a higher impurity concentration than the GaAs layer 2 is interposed between the p-type GaAs layer 2 and the n+-type GaAs layer 3. are doing. By interposing this p+ type GaAs layer 5, when a reverse bias is applied to this pulse-doped structure P, the slope of the electric field becomes steeper, and the carrier confinement effect is improved. Therefore, carriers flow between the source and drain without leaking from the channel layer, improving mutual conductance.

Furthermore, compared to FETs that use heterojunctions such as HEMTs, manufacturing is easier because only homojunctions using the same type of semiconductor are used.

Furthermore, the confinement effect is large and F
Since the ET characteristics are improved, it is effective when used in low-noise FETs.

FIG. 2 shows band diagrams of field effect transistors according to this embodiment and a conventional example. It can be seen that the energy line of the conventional example is gentle below the channel layer, but the energy line of this embodiment becomes much steeper below the channel layer. Therefore, carriers are sufficiently absorbed in the n-type GaAs layer 3 which is the channel layer.
This improves mutual conductance.

Note that the present invention is not limited to the above embodiments.

For example, the compound semiconductor used is not limited to GaAs. In the above embodiment, the first conductivity type is p type, and the second conductivity type is p type.
Although n-type conductivity is used as the conductivity type, the reverse conductivity type may be used.

〔Effect of the invention〕

Since the present invention is configured as described above, the effect of confining carriers in the channel layer in the pulse-doped structure is enhanced, and the characteristics of the FET such as mutual conductance are improved.

[Brief explanation of drawings]

FIG. 1 shows an ME using GaAs according to an embodiment of the present invention.
FIG. 2 is a band diagram comparing this embodiment with a conventional example, and FIG. 3 is a vertical cross-sectional view showing a field effect transistor according to the prior art. 1. Semi-insulating GaAs substrate, 2. P-type GaAs layer,
3- n+ type GaAs layer, 4...n- type GaAs layer, 5
- p+ type GaAs layer, s-=source electrode, D train electrode, G...gate electrode, P...pulse top structure.

Claims (1)

Claims: A first conductivity type buffer layer, a second conductivity type channel layer formed on the buffer layer and doped with impurities, and a second conductivity type channel layer formed on the channel layer and having a lower impurity concentration than the channel layer. In a field effect transistor having a pulse-doped structure including a cap layer of two conductivity types, a semiconductor layer of a first conductivity type having a higher impurity concentration than the buffer layer is further interposed between the buffer layer and the channel layer. Characteristics of field effect transistors.