JPH04102155A - Bus use right arbitrating system - Google Patents

Abstract

PURPOSE:To reduce signal lines by dividing bus master devices into groups, executing local arbitration by a group bus arbiter for each group and afterwards executing the arbitration of a system by a system arbiter. CONSTITUTION:Bus master devices 10-15 are divided into groups, and group arbiters 40 are provided in the respective groups. After the local arbitration is executed in the groups, the arbitration of the system is executed by a system arbiter 30. Namely, the hierarchical constitution of the arbitration is adopted. In this case, it is enough to connect the respective bus master devices 10-15 to the group bus arbiters 40. Thus, an interface signal line is shortened.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Prior art (Figure 5) Means for solving the problem to be solved by the invention (Figure 1) Working example (a) 1 Description of Examples (Figures 2 to 4) (b)
Description of Other Embodiments Effects of the Invention [Summary] Relating to a bus right arbitration method for arbitrating bus rights among a plurality of bus master devices connected to a common bus L7: Even if the number of bus master devices increases, the arbiter and interface become complicated. In order to avoid the hassle of major changes for expansion, we have created a system that includes multiple Hasmaster devices that are connected to a common bus and performs bus master operation, and a local bus for a group consisting of these multiple Bus Master devices. The system bus arbiter includes a group bus arbiter that arbitrates the right to use the bus, and a system bus arbiter that arbitrates the right to use the system bus in response to requests from the group bus arbiter and other group bus arbiters or bus master devices.

[Industrial application field]

The present invention relates to a bus right arbitration method for arbitrating bus rights among a plurality of bus master devices connected to a common bus.

In a system in which a plurality of bus master devices such as processors that perform bus master operations are connected to a common bus, the bus master devices use the common bus to transfer various data and execute processing.

At this time, since only one hash master device can use the common bus, arbitration is required when the bus use requests of the hash master devices conflict.

In recent years, the number of HAS master devices connected to a common bus has increased, and the number may be changed depending on the settings of options, etc.. FIG.

A main processor (CPU) 10, a main memory 17, a direct memory access controller (DMAC) 11,
A floppy disk controller (FPD) 12 is connected via a system bus 20.

The system bus 20 branches to a CRT bus 20a via a driver 21a, and connects a two-dimensional drawing processor 13 and a three-dimensional drawing processor 14.

In addition, the system bus 20 connects to AWS via the driver 21b.
It branches to bus 20b, and connects line adapter 15 and printer adapter 16.

In such high-speed image processing workstations, the C.P.
UIOlDMACII, FPD 12, processor 13.
14. The adapters 15 and 16 become bus master devices (hereinafter referred to as adapters) that perform bus master operations, and use the system bus 20, the CRT bus 20a, and the AWS bus 20b connected thereto.

Conventionally, each of the adapters IO to 16 has a request for the system, and the system node arbiter 30, which performs system arbitration (bus usage right arbitration), has performed all arbitration.

[Problem to be solved by the invention]

However, the conventional technology has the following problems.

■ In order to increase bus requests for each adapter, the number of interphase signals for arbitration increases.
Wiring becomes complicated.

■ System bus arbiter 30 handles all adaf.

Abita 30
This increases the load on the arbiter and increases the complexity of the arbiter.

■ In order to add more adapters, the interface of the entire system must be changed, which takes a lot of effort.

■ Even if the adapter accesses continuously, bus arbitration will be repeated, increasing the bus access time.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a bus use right arbitration system that does not make the arbiter or interface complicated even when the number of bus master devices increases, and can save the labor of making significant changes for expansion.

Another object of the present invention is to provide a bus right arbitration system that can reduce the number of path arbitrations and improve the speed of bus access.

[Means to solve the problem]

FIG. 1 is a diagram showing the principle of the present invention.

As shown in FIG. 1, the present invention provides a plurality of lotus master devices 10 to 10 that are connected to a common lotus 20 and perform lotus master operations.
15, the plurality of lotus mask devices 10 to 5; a group bus arbiter 40 that performs local lotus usage right arbitration for the group consisting of the group bus arbiter 40 and other group bus arbiters or bus master devices; The system bus arbiter 30 arbitrates the right to use the system bus according to the system bus arbiter 30.

Further, in claim (2) of the present invention, in claim (1), the group bus arbiter 40 is arranged such that when one hash master device in the group receives a request from another hash master device during the bus usage right Nm of the system. In response to this, requests to the system bus arbiter 30 are asserted continuously.

[Effect]

In the present invention, the bus master devices 10 to 15 are divided into groups, each group is provided with a group hash arbiter 40, and after local arbitration is performed within the group, the system bus arbiter 30 is configured to perform system arbitration. There is.

That is, a hierarchical structure of arbitration was adopted.

As a result, each bus mask device 10-15 only needs to be connected to the group bus arbiter 40, so the interface signal line can be short, wiring is simple, and the system bus arbiter 30 can communicate with all the bus master devices 10 to 15. Since there is no need to do this, the load is reduced and the configuration and scale of the system bus arbiter 30 can be significantly reduced.

Furthermore, since addition or deletion of a bus master device does not affect the system bus arbiter 30, the effort required to make changes is reduced.

Furthermore, after acquiring the right to use the system bus, the group bus arbiter 40 responds to requests from other bus master devices.
Since the bus is not released, the number of bus accesses is reduced and the speed of bus access is improved.

〔Example〕

(a) Description of one embodiment FIG. 2 is a block diagram of one embodiment of the present invention, and FIG. 3 is a block diagram of the group bus arbiter.

In the figure, the same parts as shown in Figures 1 and 5 are:
40a, 4°b, 40c are each group bus arbiters, each having two adapters,
That is, DMACII and FPD 12, two-dimensional drawing processor 13, three-dimensional drawing processor 14, and line adapter 15.
and printer adapter 16, arbitrates local bus requests BRQI and BRQ2 from these, asserts system bus request BUSREQ to system bus arbiter 30, and receives system bus ground BUS GRANT from system bus arbiter 30. local bus ground) BGTI and BGT2 are asserted to these.

The system hash arbiter 3o arbitrates the system hash request BUSREQ of each group of the CPIJIO1 and the large group hash arbiter 40a0c (7), and assigns the system bus blunt BUS GRANT to them.

In Figure 3, each group bus arbiter 4°a to 40°
c is composed of a local arbiter 4oo, a lotus request generation circuit 401, and a local bus ground generation circuit 402.

Note that the first adapter (for example, the line adapter 15) asserts the first bus request BRQl, receives the first bus ground (BGTI), and the second adapter (for example,
The printer adapter 16) makes the second bus request BRQ.
2 is asserted to receive the second path ground BGT2, and within the group, the first adapter has a higher priority.

The local arbiter 400 arbitrates between local bus requests BRQ1 and BRQ2 and generates an intra-group ground signal BGT, and has the following configuration.

That is, when the inverted intra-group ground signal *BGT is at a high level, the first antge~)Al which passes through the first local hash request BRQI and asserts the first set signal 5ETBRQI-BGT; Set by set signal +5ET-BRQl-BGT, inverted first
The local bus request * is reset by BRQ1,
A first flip-flop F1 that asserts the first intra-group ground signal +BRQI-BCT, and a second local bus request BRQ2 when the inverted intra-group ground signal *BGT and the inverted first bus request *BRQ1 are at high level. and the second set signal 5ET-
Second AND gate A asserting BRQ2-BGT
2 and the second set signal 5ET-BRQ2-BGT, the inverted second local bus request *BR
A second flip-flop F2 that is reset by Q2 and asserts the second intra-group ground signal +BRQ2-BGT, and the first and second intra-group ground signals +BR
A first OR game that takes the OR of QI~BGT, +BRQ2BGT, inverts it, and asserts the inverted intra-group ground signal *BGT) R1, and the first and second intra-group ground signals +BRQI-BGT, +BRQ2B.
It has a second OR gate R2 that takes the OR of GT and asserts the intra-group ground signal BGT.

The bus request generation circuit 401 generates a system bus request BUSR in response to the intra-group ground signal *BGT.
The EQ is asserted by the system bus arbiter 30, and has the following configuration.

That is, the first and second set signal elements 5ET-BRQl-E
OR gate R3 which takes the OR of GT, ±5ET-BRQI-BGT and issues an inverted gate output, and the third AND gate A3 which takes the AND of the inverted intra-group ground signal *BGT and the gate output of OR gate R3; Set by ground signal *BGT, AND gate A
It is reset with the output of 3, and the system bus request +B
Third flip-flop F3 asserting USREQ
and has.

The o-power 7L/bus ground generation circuit 402 receives the system bus blunt +BUS from the system bus arbiter 30.
GRANT connects the local bus ground +BGTI, +B to the adapter given the intra-group ground signal.
GT2 is asserted, and the fourth AND is performed by ANDing the system bus blunt + BUS GRANT and the first in-group ground signal + BRQI-BGT, and asserting the first local bus ground + BGTI to the first adapter hair. A gate A4, a fifth AND gate A5 which ANDs the system bus blunt BUSGRANT and the second intra-group ground signal BRQ2-BGT, and asserts the second local bus ground BGT2 to the second adapter. has.

FIG. 4 is a time chart diagram of one embodiment of the present invention.

The first and second adapters are local bus request BRQ
I, BRQ2 as group lotus arbiter 40 (40a~
40c) to the local arbiter 400.

In the local arbiter 400, priority is given to the first adapter, but if the request BRQI of the first adapter comes first as shown in FIG. child5ET-BRQI-BGT
is asserted, the first flip-flop Fl is set, and the first in-group ground l-+BRQ1-BGT is issued, and the inverted intra-group ground signal *BGT and intra-group ground signal 10BGT are output from the OR gates R1 and R2. Assert.

This causes intra-group arbitration and turns off the second AND gate A2 for the second adapter.

The intra-group ground signal 10BGT sends the third flip-flop F3 of the bus request generation circuit 401, and issues a system bus request +BUSREQ to the system bus arbiter 3o.

The system bus arbiter 30 arbitrates this system bus request and issues a system bus grant ->-BUS GRANT when granting the usage right.

This is received by the local bus ground generation circuit 402, and in this case, the AND gate A of the in-group ground signal is turned on.
4 provides local bus ground +BGTI to the first adapter, allowing use of the common bus 20.

When the local bus request BRQI is negated from the adapter, the group bus arbiter 40 negates the system bus request BUSREQ to the system bus arbiter 30, but before negating it as shown in FIG. If local bus request BRQ2 is asserted from the adapter, the first
By negating the local bus request BRQI of the adapter, the second set signal +5ET-BRQI-BGT is asserted from the second adapter A2, and the bus request generation time! The third AND gate A3 is closed through the OR gate R3 of 401, and the third flip-flop F3 is prevented from being reset (.

Therefore, the bus request to the system + BtJSRE
Q is not negated and the local path ground BGT to the second adapter is asserted by the fifth AND gate A5.

In this way, when the bus master operations of adapters in a group occur continuously, the bus master operation of the next adapter is performed without releasing the bus, thereby reducing the number of bus arbitrations and reducing bus access. It is possible to speed up the process.

Also, if the adapter is a local bus request BRQI,
BRQ2, bus ground +BGTI, +BGT2, and causes the group bus arbiter 40 to perform arbitration within the group, and as a result, the system bus arbiter 3
Since a system bus request is issued to 0 and a system bus blunt is obtained, arbitration can be layered, simplifying the wiring of the entire system, downsizing the system bus arbiter, and increasing the number of adapters. For this purpose, it is only necessary to change the configuration up to the group bus arbiter 40, and there is no need to change the entire system.

0)) Description of other embodiments In addition to the embodiments described above, the present invention can be modified as follows.

(2) Although the priority order of the group bus arbiter is fixed to one adapter, for example, a usage order circuit may be provided and the priority order may be sequentially changed and assigned to the adapters within the group.

■ For the system bus arbiter, CPLII in Figure 2
Adapters that do not go through the group bus arbiter may be mixed, as shown in FIG. 1, or all adapters may be connected through the group bus arbiter, as shown in FIG.

(2) At least one group bus arbiter may be connected to the system bus arbiter, and the others may be adapters or other group bus arbiters.

■ The number of adapters in the group bus arbiter is 2.
It is not limited to one person, but may be more than one.

Although the present invention has been described above using examples, the present invention can be modified in various ways according to the gist of the present invention, and these are not excluded from the present invention.

〔Effect of the invention〕

According to the present invention, the birch described above has the following effects.

■ Bus master devices are divided into groups, and the group bus arbiter performs local arbitration for each group, and then the system bus arbiter performs system arbitration, so the interface signal line for arbitration can be shortened. Signal lines can be reduced.

■ Since all bus master devices issue requests to the system bus arbiter via the group bus arbiter, the load on the system bus arbiter is reduced, and the scale of the system bus arbiter can be significantly reduced. Even if it is provided, the scale of the entire arbiter can be reduced.

■ Adding or removing a bus master device affects only the group bus arbiter and not the system bus arbiter, which reduces the effort required to make changes.

(2) In claim (2), since the bus is not released when the bus master devices in the group perform successive bus master operations, the number of buzz arbitrations can be reduced and the bus access speed can be improved.

20- common lotus, 30-system bus arbiter, 40-Group bus arbiter.

Claims (2)

[Claims] (1) A plurality of bus master devices (10 to 15) connected to a common bus (20) and performing bus master operations, and local bus usage right arbitration for a group consisting of the plurality of bus master devices (10 to 15). a system bus arbiter (30) that performs system bus usage right arbitration in response to requests from the group bus arbiter (40) and other group bus arbiters or bus master devices;
). (2) The group bus arbiter (40) sends the system bus arbiter (30) to the system bus arbiter (30) in response to a request from another bus master device while one bus master device in the group is acquiring the right to use the system bus. 2. The bus use right arbitration method according to claim 1, wherein the bus use right arbitration method continues to assert the request.