JPH04102959A - Exception processing system for information processor - Google Patents

Abstract

PURPOSE:To easily specify the address of a coprocessor instruction generating an exception by saving contents to be stored by a storage means in an exception processing saving area in a main storage at the time of informing exception detection from the coprocessor to the master processor. CONSTITUTION:This exception processing system is provided with a storage means 3 for storing the address of an instruction, the 1st control means 11 for storing the address including a coprocessor instruction extracted by the master processor 1 in the storage means 3 and the 2nd control means 12 for saving the contents of the means 3 to the exception processing saving area 41 of the main storage device 4 when exception detection is informed from the coprocessor 2 to the master processor 1. Even when exceptional operation is generated in the coprocessor instruction and the master processor 1 has already executed processing the coprocessor instruction to be the cause of the exception, the address including the coprocessor instruction can be known from the contents of the area 41.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an exception handling method for an information processing device, and particularly to an exception handling method for an information processing device that has a coprocessor subordinate to a master processor and performs parallel processing. [Technology] In conventional exception handling methods for information processing devices, when a master processor is notified of an exception from a coprocessor, it stores the address of the instruction being executed by the master processor in a save area for exception handling in main memory. He had evacuated.

[Problem to be solved by the invention]

In the exception handling method of the conventional information processing device described above,
In a system where the master processor and coprocessor operate in parallel, when the master processor is notified of an exception by the coprocessor, it is likely already processing after the coprocessor instruction that caused the exception; The drawback is that the address of the instruction that caused the operation cannot be determined from the contents of the save area for exception handling in the main memory.

[Means to solve the problem]

In the exception handling method of the information processing device of the present invention, the master processor of the central processing unit sequentially fetches and executes instructions, has a subordinate coprocessor take over the execution of the fetched coprocessor instructions, and fetches instructions subsequent to the coprocessor instructions. In an information processing apparatus that performs parallel processing, the information processing apparatus includes a storage means for storing an address of the instruction, and a first storage means for storing an address at which the instruction exists when the master processor retrieves the coprocessor instruction. and a second control means for saving the contents of the storage means to a save area for exception handling in a main storage device when the master processor is notified of exception detection from the coprocessor.

〔Example〕

Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a flowchart for explaining the operation of this embodiment.

In FIG. 1, a master processor 1, a coprocessor 2 subordinate to the master processor 1, a storage means 3 for storing the address of a coprocessor instruction when the master processor 1 retrieves the instruction, and a main storage device. 4.

The master processor 1 also has a first control means 11 that stores an address where the instruction exists in the storage means 3 in advance when executing a coprocessor instruction, and a main storage device that stores an address where the instruction exists in the storage means 3 when the master processor 1 is notified of an exception from the coprocessor 2. Coprocessor counter save area 411 in the exception save area 41 for exception handling in No. 4
The second control means 12 saves the contents of the storage means 3.
Contains. The main storage device 4 includes an exception save area 41 which is a save area for exception processing when an exception occurs, and the exception save area 41 further includes a coprocessor counter save area 411 for saving the contents of the storage means 3. Contains.

Next, the operation of this embodiment will be explained with reference to FIGS. 1 and 2.

As shown in step 210, the master processor 1 determines whether or not the instruction is a coprocessor instruction before executing the instruction, and if it is a coprocessor instruction, the master processor 1 uses a control means to store in advance the address where the instruction exists. 11, the program counter (
instruction address) in the storage means 3, and step 230
Execute the command as shown. At this time, if the instruction is a coprocessor instruction, it is executed by the coprocessor 2.

Next, as shown in step 240, the subsequent processing continues unless an exception occurs, and if the master processor 1
Alternatively, if an exception occurs on the coprocessor 2, as shown in step 250, the master processor 1 stores the register information (context) of the master processor 1 or coprocessor 2 at that time in the exception save area in the main memory 4. 41.

Next, as shown in step 260, the master processor 1
The control means 12 causes this exception to be detected by the master processor 1.
It is determined whether the occurrence occurred in coprocessor 2 or coprocessor 2, and if it occurred in coprocessor 2, step 27
The value of the storage means 3 is saved to the coprocessor counter save area 411 in the exception save area 41 as indicated by 0. At this time, since the content of the storage means 3 is the address where the coprocessor instruction exists, the address of the coprocessor instruction is stored in the exception save area 41.

In this way, even if an exception occurs with a coprocessor instruction and the master processor 1 has already processed the coprocessor instruction that caused the exception, the address where the coprocessor instruction exists will be stored in the exception save area 4. You can learn about the contents.

〔Effect of the invention〕

As explained above, the present invention stores the address where the instruction exists when the master processor retrieves the coprocessor instruction in the storage means for storing the address of the instruction, and the master processor detects an exception from the coprocessor. By saving the contents stored by the storage means in the save area for exception handling in the main memory when notified, the address of the Cobroseza instruction that caused the exception can be easily identified from the contents of the save area. This has the effect of allowing prompt investigation of failures.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a flowchart 1 to 1 for explaining the operation of this embodiment. ]... Master processor, 2... Cobroseza, 3...
- Storage means, 4... main storage device.

Claims (1)

[Claims] In an information processing device, a master processor of a central processing unit sequentially fetches and executes instructions, causes subordinate coprocessors to execute the fetched coprocessor instructions on behalf of the master processor, and fetches instructions subsequent to the coprocessor instructions to perform parallel processing,
storage means for storing the address of the instruction; first control means for storing in the storage means the address at which the instruction exists when the master processor retrieves the coprocessor instruction; An exception handling method for an information processing device, comprising: second control means for saving the contents of the storage means to a save area for exception processing in a main memory when notified of exception detection from a processor.