JPH04103219A - Ecl type logic circuit - Google Patents

Abstract

PURPOSE:To improve the increase in a delay time due to a load capacitor by providing a load capacitor connected in parallel with a load resistor of a 1st transistor(TR) and a coupling resistor between collectors of 1st and 2nd TRs. CONSTITUTION:A load capacitor C1 connected in parallel with a load resistor R1 of a TR Q1 and a coupling resistor R3 connected between collectors of TRs Q1, Q2 are provided to the circuit. When the resistance of the coupling resistor R3 is selected infinite, a potential V1 shows an exponential attenuation waveform with a time constant comprising the load resistor R1 and the load capacitor C1, and a potential V2 shows a step response waveform by a load resistor R2 in the potentials V1, V2 of the collectors of the TRs Q1, Q2. When the resistance of the coupling resistor R3 is selected to be a definite value, a potential V2 shows an intermediate waveform between the waveforms of the said potentials V1, V2. Thus, a waveform having overshoot is obtained as an output potential VOUT of the logic circuit. Thus, the delay time of the logic circuit is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is applied to an ECL type logic circuit configured within a semiconductor integrated circuit.

〔overview〕

The present invention provides an ECL type logic circuit consisting of a current switch circuit and an emitter follower circuit that takes out the output of the current switch circuit. This is an improvement over the increase in delay time of the logic circuit when it becomes heavy.

[Conventional technology]

In the conventional ECL type logic circuit, as shown in Fig. 7, the emitters are commonly connected to a constant current source, and the respective collectors are connected to a power supply potential (ground potential) through load resistors R1 and R2. The transistor Q3 has a base connected to the collector of the transistor Q2 and a collector connected to a power supply potential. The emitter of transistor Q3 is normally connected to a constant potential V through a load resistor RL. CL represents the load capacity of this circuit.

Next, the operation of this conventional example will be explained. When the input potential vl applied to the base of the transistor Q1 is high with respect to the reference potential v3 applied to the base of the transistor Q2, the transistor Q is turned on and Q2 is turned off, and the collector C2 becomes a high potential, and the potential VH is applied to the emitter of the transistor Q3. When the input potential v1 is a low potential with respect to the reference potential vR, the transistor Q1 is "off" and the transistor Q2 is "on", the collector of the transistor Q2 has a low potential, and the potential VL is output to the emitter.

When there is a transient change from Vi to VR to Vt>v, the emitter potential of transistor Q3, that is, the output potential V, as shown by the solid line in FIG. U.

changes from VL to V after the delay time tPd has elapsed.

Vi>v, to Vt<Val: When changing, the output potential V, as shown by the dotted line in FIG. , T changes from vH to VL after tPd elapses.

[Problem to be solved by the invention]

In this conventional ECL type logic circuit, when the load capacitance CL increases, the output potential V. This has the disadvantage that the waveform of the UT becomes dull and the delay time increases, causing a delay in the response of the next stage logic circuit.

SUMMARY OF THE INVENTION An object of the present invention is to provide an ECL type logic circuit in which increase in delay time due to load capacitance is improved.

[Means to solve the problem]

The present invention provides a current switch circuit composed of first and second transistors whose emitters are commonly connected to a constant current circuit and whose collectors are respectively connected to a power supply potential via a load resistor; a third transistor connected to the collector of the transistor whose collector is connected to a power supply potential; a load capacitor connected in parallel to the load resistor of the first transistor; and a coupling resistor connected between the collectors of the second transistor.

Further, the present invention is characterized in that the circuit network constituted by the load resistors of the first and second transistors and the coupling resistor is replaced with an equivalent impedance network.

[Effect]

When the coupling resistance is infinite, that is, when no coupling resistance is inserted, the operating waveform of the collector potential of the first transistor becomes an exponential waveform with a time constant determined by the load resistance and the inserted load capacitance. The operating waveform of the collector potential of the second transistor becomes a step response waveform according to its load resistance, and the direction of change thereof is opposite to that of the collector potential of the first transistor. When the coupling resistance is finite, the operating waveform of the collector potential of the second transistor, which is the output terminal of the current switch circuit, is
The step response waveform is superimposed on the exponential waveform, and has an overshoot.

Therefore, by setting a constant so that this overshoot voltage is equal to or higher than the logic level, the time to reach the logic level becomes faster, and the delay time can be shortened.

Note that the resistor network composed of two load resistors and a coupling resistor may be replaced with an impedance network such as another resistor network by performing Δ-Y conversion, for example.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

In the present embodiment, the emitters are commonly connected to the negative power supply v■ through the constant current source 11, and the collectors are connected to the power supply potential (here, the ground potential) through the load resistors R1 and R2, respectively.
A current switch circuit is constructed of first and second transistors Ql and Q2, which are NPN bipolar transistors connected to the base of the transistor Q2 and whose bases are respectively applied with an input potential v1 and a reference potential vR; The collector is connected to a power supply potential (ground potential), the emitter is connected to a constant potential V via a load resistor RL, and the power supply potential (ground potential) via a load capacitor CL, and the emitter is connected to an output potential V
. In an ECL type logic circuit equipped with a third transistor Q3 made of an NPN type bipolar transistor for taking out U, a load capacitor C1 connected in parallel to the load resistor R1 of the transistor Q1 is characterized by the present invention. and a junction resistor R3 connected between the collectors of the transistor Q and Q2.

Next, the operation of the present embodiment will be explained.

Load resistor R2 of transistor Q2 generates a normal output waveform, and load resistor R1 and load capacitor CI of transistor Q+ generate a correction waveform. The output waveform and the correction waveform are coupled by a coupling resistor R3.

Next, the operation will be described with reference to operation waveforms, taking as an example the case where the input potential v1 changes from V, <V, to Vi >VR.

When the coupling resistance R3 is infinite, the transistor Q.

The collector potentials V1 and Vl of Q2 are as shown in FIG. 2(a), where Vl is the load resistance R1 and the load capacitance C
1, and Vl becomes an exponentially decaying waveform due to the time constant formed by V1, and Vl becomes a step response waveform due to the load resistance R2. When the coupling resistance R5 is finite, ■2 is shown in Figure 2 (b
), a waveform intermediate between Vt and v2 in the case of FIG. 2(a) is obtained. If the coupling resistance R3 is finite and the input vi changes from Vt > V, 1, then v2
The result will be as shown in the figure. Output potential V. U, is an emitter follower constituted by the transistor Q3 and the load resistor R2, and outputs Vovr=Va VBE which is lower than v2 by the emitter-base potential VBE of the transistor Q3.

Therefore, the output potential V of the ECL type logic circuit of this embodiment
. As for U, a waveform with an overshoot as shown in FIG. 4 is obtained. When the load on the logic circuit becomes heavy, in the conventional circuit shown in FIG. 7, the output potential V decreases as shown by the dotted line in FIG. Whereas the waveform of U becomes dull, in this embodiment, the rising and falling waveforms of the output can be improved as shown by the solid line.

FIG. 6 is a circuit diagram showing a second embodiment of the present invention. In this second embodiment, the resistors R1, R2 and R3 of the first embodiment are
The circuit is completely equivalent as a circuit. The resistances rl, r2, and r3 are given by the formulas shown below.

rl=R2R3/(R1+R2+R3)r2=RaR+
/(R+ +R2+R3)rs=RIR2/(R1+R
2+R3) If R+ =Ra =R3=R, then r, =
By analogy with the fact that r, = r3 = R/3, the second embodiment has the advantage that the resistor used can be set to a low value.

By using whichever of the first and second embodiments is more advantageous in terms of layout, it is possible to reduce the circuit area.

〔Effect of the invention〕

As explained above, the present invention provides an output waveform correction circuit composed of a resistor and a capacitor between the complementary outputs of an ECL type logic circuit, thereby reducing the dullness of the output waveform when the output load becomes heavy. This correction has the effect of improving the delay time of the logic circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. FIGS. 2(a) and 2(b) are characteristic diagrams showing collector potential waveforms of the complementary transistors. FIG. 3 is a characteristic diagram showing the collector potential waveform of the complementary transistor. FIG. 4 is a characteristic diagram showing the output potential waveform. FIG. 5 is a characteristic diagram showing the output potential waveform in comparison with a conventional example. FIG. 6 is a circuit diagram showing a second embodiment of the present invention. FIG. 7 is a circuit diagram showing a conventional example. FIG. 8 is a characteristic diagram showing the output potential waveform. C1, CL...Load capacity, 11... Constant current source, Ql
, Q2, Q3...transistor, R1, R2, RL
...Load resistance, R8...Coupling resistance, rt, r=
, r,...resistance, Vl, V2... collector potential,
■,... Negative power supply, Vi... Input potential, VOI...
Output potential, VII... reference potential, Vt... constant potential. Patent application submitted by NEC Corporation, agent: Nao Ide, Takato - Real 3rd Purpose E! 3 Σ Ri兇 3 Figures - Examples 4 Figures - Examples/Conventional Dali, ¥15 Figure 2 Figure 6

Claims (1)

[Claims] 1. A current switch circuit composed of first and second transistors whose emitters are commonly connected to a constant current circuit and whose collectors are respectively connected to a power supply potential via a load resistor, and a base. a third transistor whose collector is connected to the collector of the second transistor and whose collector is connected to a power supply potential; a load capacitor connected in parallel to the load resistor of the first transistor; , and a coupling resistor connected between the collectors of the first and second transistors. 2. In the ECL type logic circuit according to claim 1, the circuit network constituted by the load resistors of the first and second transistors and the coupling resistor is replaced with an equivalent impedance network. ECL type logic circuit.