JPH04117724A - Ecl circuit - Google Patents
Ecl circuitInfo
- Publication number
- JPH04117724A JPH04117724A JP23305290A JP23305290A JPH04117724A JP H04117724 A JPH04117724 A JP H04117724A JP 23305290 A JP23305290 A JP 23305290A JP 23305290 A JP23305290 A JP 23305290A JP H04117724 A JPH04117724 A JP H04117724A
- Authority
- JP
- Japan
- Prior art keywords
- output
- transistor
- circuit
- load capacitor
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 abstract description 7
- 238000007599 discharging Methods 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 1
Landscapes
- Logic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はＥＣＬ回路に関し、 する。[Detailed description of the invention] [Industrial application field] The present invention relates to an ECL circuit, do.
従来のＥＣＬ回路の出力部は、第２図に示すようなエミ
ッタ・フォロア（Ｅ−Ｆ））ランジスタ２０と、Ｅ−Ｆ
抵抗２１とで構成していた。The output section of the conventional ECL circuit consists of an emitter follower (E-F) transistor 20 and an E-F transistor as shown in FIG.
It consisted of a resistor 21.
入力部は、入力トランシスタ１６．リファレンストラン
ジスタ１７．定電流源１５．コレクタロード抵抗１８．
１９からなり、入力トランジスタ１６のベースは入力端
子２５が接続され、リファレンストランジスタ１７のベ
ースにハ基準！圧ＶＲＥＦが印加される。最高電位２３
．最低電位２４との間に前記出力部、入力部が設けられ
る。The input section includes an input transistor 16. Reference transistor 17. Constant current source 15. Collector load resistance 18.
19, the base of the input transistor 16 is connected to the input terminal 25, and the base of the reference transistor 17 is connected to the base of the reference transistor 17. Pressure VREF is applied. Highest potential 23
．． The output section and the input section are provided between the lowest potential 24 and the lowest potential 24.
従来のＥＣＬ回路において、出力電位の立下り時間は、
出力負荷容量２２の電荷の放電をＥ−Ｆ抵抗２１で行う
ため、立ち上り時間に比べより犬なる時間を要するとい
う欠点があり、また出力部特に出力回路に関
荷容量Ｃが大きいほどその差が大きくなる欠点力ある。In the conventional ECL circuit, the fall time of the output potential is
Since the charge of the output load capacitance 22 is discharged by the E-F resistor 21, there is a drawback that it takes a longer time than the rise time, and the difference becomes larger as the load capacitance C is larger in the output section, especially in the output circuit. There is a disadvantageous power that grows.
本発明の目的は、前記欠点が解決され、立ち１つ時間、
立ち下り時間を短縮したＥＣＬ回路を扶供することにあ
る。It is an object of the present invention to solve the above-mentioned drawbacks and to
The purpose of the present invention is to provide an ECL circuit with a shortened fall time.
本発明のＥＣＬ回路の構成は、差動増幅回路の第１の出
力をベースとし、かつ所定のインピータンスを負荷とす
る第１のエミッタ・フォロア・トランジスタと、前記差
動増幅回路の第２の出力をベースとする第２のエミッタ
・フォロア・トランジスタと、前記第１のエミッタ・フ
ォロア・トランジスタのエミッタをコレクタに、前記イ
ンピータンスの一端をエミッタに、前記第２のエミッタ
・フォロア・トランジスタのエミッタをベースにそれぞ
れ接続してなる第３のトランジスタを設は前記第３のト
ランジスタのコレクタを出力端子となしたことを特徴と
する。The configuration of the ECL circuit of the present invention includes a first emitter follower transistor which is based on the first output of the differential amplifier circuit and has a predetermined impedance as a load, and a second emitter follower transistor of the differential amplifier circuit. a second emitter follower transistor based on the output, the emitter of the first emitter follower transistor as the collector, one end of the impedance as the emitter, and the emitter of the second emitter follower transistor as the emitter; The third transistor is connected to the base thereof, and the collector of the third transistor is used as an output terminal.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例のＥＣＬ回路の回路図である
。FIG. 1 is a circuit diagram of an ECL circuit according to an embodiment of the present invention.
第１図において、本実施例のＥＣＬ回路は、定電流源１
と入力トランジスタ２と、リファレンストランジスタ３
と、コレクタロード抵抗４．５と、出力Ｅ−Ｆ）ランジ
スタロと、差動出力Ｅ−Ｆトランジスタ７と、出力負荷
容量放電用トランジスタ８と、電流制限用インピーダン
ス９と、出力負荷容１１０を接続する出力端子１４と、
最高電位１１ラインと、最低電位１２ラインと、入力端
子１３とを備えている。In FIG. 1, the ECL circuit of this embodiment has a constant current source 1
, input transistor 2, and reference transistor 3
, collector load resistance 4.5, output E-F) transistor, differential output E-F transistor 7, output load capacitance discharge transistor 8, current limiting impedance 9, and output load capacitor 110 are connected. an output terminal 14 for
It includes 11 lines of highest potential, 12 lines of lowest potential, and an input terminal 13.
ここで、出力端子１４の電位が、高電位から低電位に変
化するとき、同時に差動出力Ｅ−Ｆ）ランシスタフのベ
ース電位が上昇しており、圧力負荷容量１０の放電用ト
ランジスタ８のコレクタ電流が増加し、出力負荷容量１
０の放電を早くし、その結果立ち下り時間が短かくなる
。Here, when the potential of the output terminal 14 changes from a high potential to a low potential, at the same time, the base potential of the differential output E-F) Runsy Stuff increases, and the collector current of the discharge transistor 8 of the pressure load capacity 10 increases. increases, output load capacity 1
0 discharge is made faster, resulting in a shorter fall time.
以上の説明においては、バッファ回路に使用するものと
したが、これに限られることなく、インバータ回路でも
、多入力ＯＲ回路ても、差動出力をとり得るＥＣＬ回路
であれば、同様の効果が得らｈる。In the above explanation, it is assumed that the circuit is used for a buffer circuit, but it is not limited to this, and any ECL circuit that can take a differential output can have the same effect, whether it is an inverter circuit or a multi-input OR circuit. I get it.
以上説明したように本発明は、出力負荷容量の放電用ト
ランジスタと、一端が出力負荷容量放電用トランジスタ
のエミッタに接続し、他端を最低電位に接続するインピ
ーダンスとにより、ＥＣＬ回路の立ち下り時間を短かく
できる効果がある。As explained above, the present invention uses a transistor for discharging the output load capacitance and an impedance whose one end is connected to the emitter of the transistor for discharging the output load capacitance, and the other end is connected to the lowest potential. This has the effect of making it shorter.
第１図は本発明の一実施例のＥＣＬ回路の回路図、第２
図は従来のＥＣＬ回路の回路図である。
１．１５・・・・定電流源、２，１６・・・・入力トラ
ンジスタ、３．１７・・・・リファレンストランジスタ
、４，５，１８．１９・・・・コレクタロード抵抗、６
．２０・・・出カニミッタ・フォロア（Ｅ −Ｆ）トラ
ンジスタ、７・・・・・差動出力Ｅ−Ｆ）ランジスタ、
８・・・・・出力負荷容量放電用トランジスタ、９・・
・・電流制限用インピータンス、１０，２２・・・・・
・出力負荷容量、１１．２３・・・・・最高電位、１２
゜最低電位、
１３゜
５・・
・入力端子、
１４゜
２６・・・・
出力端子、
１・・
・Ｅ−Ｆ抵抗。FIG. 1 is a circuit diagram of an ECL circuit according to an embodiment of the present invention, and FIG.
The figure is a circuit diagram of a conventional ECL circuit. 1.15...constant current source, 2,16...input transistor, 3.17...reference transistor, 4,5,18.19...collector load resistor, 6
．． 20...Output limiter follower (E-F) transistor, 7...Differential output E-F) transistor,
8... Output load capacitance discharge transistor, 9...
... Current limiting impedance, 10, 22...
・Output load capacity, 11.23... Maximum potential, 12
゜Minimum potential, 13゜5... - Input terminal, 14゜26... Output terminal, 1... - E-F resistance.
Claims (1)
ンピーダンスを負荷とする第１のエミッタ・フォロア・
トランジスタと、前記差動増幅回路の第２の出力をベー
スとする第２のエミッタ・フォロア・トランジスタと、
前記第１のエミッタ・フォロア・トランジスタのエミッ
タをコレクタに、前記インピーダンスの一端をエミッタ
に、前記第２のエミッタ・フォロア・トランジスタのエ
ミッタをベースにそれぞれ接続してなる第３のトランジ
スタを設け、前記第３のトランジスタのコレクタを出力
端子となしたことを特徴とするＥＣＬ回路。A first emitter follower based on the first output of the differential amplifier circuit and loaded with a predetermined impedance.
a second emitter follower transistor based on a second output of the differential amplifier circuit;
A third transistor is provided in which the emitter of the first emitter follower transistor is connected to the collector, one end of the impedance is connected to the emitter, and the emitter of the second emitter follower transistor is connected to the base, An ECL circuit characterized in that the collector of the third transistor is used as an output terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23305290A JPH04117724A (en) | 1990-09-03 | 1990-09-03 | Ecl circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23305290A JPH04117724A (en) | 1990-09-03 | 1990-09-03 | Ecl circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04117724A true JPH04117724A (en) | 1992-04-17 |
Family
ID=16949045
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23305290A Pending JPH04117724A (en) | 1990-09-03 | 1990-09-03 | Ecl circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04117724A (en) |
-
1990
- 1990-09-03 JP JP23305290A patent/JPH04117724A/en active Pending
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