JPH04103649U - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPH04103649U JPH04103649U JP1991003721U JP372191U JPH04103649U JP H04103649 U JPH04103649 U JP H04103649U JP 1991003721 U JP1991003721 U JP 1991003721U JP 372191 U JP372191 U JP 372191U JP H04103649 U JPH04103649 U JP H04103649U
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- lead wire
- thin lead
- metal film
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5438—Dispositions of bond wires the bond wires having multiple connections on the same bond pad
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/59—Bond pads specially adapted therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/932—Plan-view shape, i.e. in top view
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/934—Cross-sectional shape, i.e. in side view
Landscapes
- Wire Bonding (AREA)
Abstract
(57)【要約】
【目的】 半導体装置の電流容量を大きくする。
【構成】 半導体領域1bとこの主面上に形成された電
極3とを有し、この電極3にリード細線4を接続する時
に、離間させて少なくとも2つの接続部4a、4bを設
ける。
(57) [Summary] [Purpose] To increase the current capacity of a semiconductor device. [Structure] The device has a semiconductor region 1b and an electrode 3 formed on the main surface thereof, and when connecting a thin lead wire 4 to the electrode 3, at least two connecting portions 4a and 4b are provided at a distance.
Description
【0001】0001
本考案はトランジスタやサイリスタ等の半導体装置に関する。 The present invention relates to semiconductor devices such as transistors and thyristors.
【0002】0002
トランジスタやサイリスタでは、半導体基板の一方の主面に絶縁膜が形成され 、主電極はこの絶縁膜に形成された開口を通じて半導体基板に接続されている。 また、主電極にはリード細線の一端が接続されて外部リード等と電気的に接続さ れている。ところで、近年これらの半導体装置の大電力化はめざましいものがあ り、このため装置の大電流容量化が急務となっている。 In transistors and thyristors, an insulating film is formed on one main surface of the semiconductor substrate. , the main electrode is connected to the semiconductor substrate through an opening formed in this insulating film. In addition, one end of the thin lead wire is connected to the main electrode and electrically connected to external leads, etc. It is. Incidentally, in recent years, there has been a remarkable increase in the power consumption of these semiconductor devices. Therefore, there is an urgent need to increase the current capacity of the device.
【0003】 そこで、本考案は、大電流容量化を実現できる新規な構造の半導体装置を提供 することを目的としている。0003 Therefore, this invention provides a semiconductor device with a new structure that can realize large current capacity. It is intended to.
【0004】0004
上記目的を達成するための本考案は、半導体領域と、前記半導体領域の主面に 形成された電極とを有し、同一のリード細線が前記電極に対して互いに離間した 2箇所以上で接続されていることを特徴とする半導体装置に係わるものである。 To achieve the above object, the present invention includes a semiconductor region and a main surface of the semiconductor region. electrodes formed therein, and identical lead wires are spaced apart from each other with respect to said electrodes. The present invention relates to a semiconductor device characterized by being connected at two or more points.
【0005】[0005]
本考案の半導体装置によれば、電極に対して同一のリード細線が2箇所以上で 接続されているので、リード細線及びリード細線に達する半導体領域及び電極内 の電流通路の電流密度を低減できる。 According to the semiconductor device of the present invention, the same thin lead wire is connected to the electrode at two or more locations. Because they are connected, the thin lead wire and the inside of the semiconductor area and electrode that reach the thin lead wire The current density of the current path can be reduced.
【0006】[0006]
以下、図1及び図2を参照して本考案の一実施例に係わる半導体装置を説明す る。 Hereinafter, a semiconductor device according to an embodiment of the present invention will be explained with reference to FIGS. 1 and 2. Ru.
【0007】 本実施例の半導体装置は、半導体基板1と絶縁膜2と金属電極3とリード細線 4とを有する。半導体基板1はP形領域1aと、半導体基板1の一方の主面にそ の上面を露出させてP形領域1aに隣接包囲されているN+ 形領域1bとを有す る。絶縁膜2はシリコン酸化膜等から成り、これに形成された開口5からはN+ 形領域1bの上面が露出する。金属電極3は、相対的に薄い第1の金属膜6と相 対的に厚い第2の金属膜7から成る。第1の金属膜6は、P形領域1aとN+ 形 領域1bとのPN接合8が半導体基板1の上面に露出している部分よりも外側ま で延在し、周知のフィールドプレートとして機能する。第2の金属膜7は平面的 に見てN+ 形領域1bの内側に形成されている。The semiconductor device of this embodiment includes a semiconductor substrate 1 , an insulating film 2 , a metal electrode 3 , and a thin lead wire 4 . Semiconductor substrate 1 has a P-type region 1a and an N + -type region 1b which is surrounded by and adjacent to P-type region 1a with its upper surface exposed on one main surface of semiconductor substrate 1. The insulating film 2 is made of a silicon oxide film or the like, and the upper surface of the N + type region 1b is exposed through the opening 5 formed therein. The metal electrode 3 consists of a relatively thin first metal film 6 and a relatively thick second metal film 7. The first metal film 6 extends to the outside of the portion where the PN junction 8 between the P type region 1a and the N + type region 1b is exposed on the upper surface of the semiconductor substrate 1, and functions as a well-known field plate. . The second metal film 7 is formed inside the N + type region 1b when viewed in plan.
【0008】 リード細線4は、約400μmの直径を有するAl(アルミニウム)線であり 、金属電極3の第2の金属膜7に対して互いに離間した2箇所で接続されている 。更に詳述すると、リード細線4は、図2から明らかなように平面形状四角形の 第2の金属膜7の対角線上に配設されており、第2の金属膜7に対する第1の接 続部4a及び第2の接続部4bはこの対角線上に位置する。リード細線4の延在 する方向における第1の接続部4aの長さL1 、第1の接続部4aと第2の接続 部4bとの間の長さL2 及び第2の接続部4bの長さL3 はそれぞれ約950μ mに設定されている。リード細線4はキャピラリによってその径方向に押圧され て第2の金属膜7に接続されるので、第1及び第2の接続部4a、4bは図1の ように扁平化してその幅Wはリード細線4の径の約2.5倍となる。本実施例で は、第2の金属膜7は2.5mm×2.5mmの略正方形の平面形状を有し、そ の対角線方向にボンディング領域9を設けるので、このボンディング領域9に幅 Wの接続部4a、4bを収めることができる。ボンディング領域9の長さはL1 とL2 とL3 の和よりも勿論長い。[0008] The thin lead wire 4 is an Al (aluminum) wire having a diameter of about 400 μm. , are connected to the second metal film 7 of the metal electrode 3 at two points spaced apart from each other. . More specifically, the thin lead wire 4 has a rectangular planar shape, as is clear from FIG. The second metal film 7 is disposed on a diagonal line, and the first contact with the second metal film 7 is The connecting portion 4a and the second connecting portion 4b are located on this diagonal line. Extension of thin lead wire 4 The length L1 of the first connecting portion 4a in the direction of The length L2 between the connecting portion 4b and the length L3 of the second connecting portion 4b are each approximately 950μ. m is set. The thin lead wire 4 is pressed in its radial direction by the capillary. Since the first and second connecting portions 4a and 4b are connected to the second metal film 7 as shown in FIG. The width W is approximately 2.5 times the diameter of the thin lead wire 4. In this example The second metal film 7 has a substantially square planar shape of 2.5 mm x 2.5 mm; Since the bonding area 9 is provided in the diagonal direction of W connection parts 4a and 4b can be accommodated. The length of the bonding region 9 is L1 It is of course longer than the sum of L2 and L3.
【0009】 本実施例の半導体装置によれば、リード細線4が電極3に対して互いに離間し た2箇所で接続されているので、従来のようにリード細線が電極に対して一点で 接続されている場合に比べて電流容量を増大することができた。この理由は第1 にリード細線4と電極3との接続部の面積が増大し、電流密度が低くなるためで あり、第2にリード細線4の接続部4a、4bが電極3の両側に離間して配設さ れているので、P形領域1aとN+ 形領域1bと電極3からリード細線4に達す る主たる電流通路が左右に分れ、それぞれの電流密度が小さくなるためと考えら れる。特に、本実施例ではリード細線4が電極3の対角線方向に張られており、 第1の接続部4aと第2の接続部4bとの間隔L2 を長くとれるので有利である 。また、第1の接続部1aと第2の接続部1bがこの間のリード部分も含めて一 直線上にあるので、スティッチボンディングを良好に行うことができる。According to the semiconductor device of this embodiment, the thin lead wire 4 is connected to the electrode 3 at two points spaced apart from each other, so unlike the conventional method, the thin lead wire 4 is connected to the electrode at one point. We were able to increase the current capacity compared to the case where the The reason for this is firstly that the area of the connection between the thin lead wire 4 and the electrode 3 increases and the current density decreases, and secondly that the connecting portions 4a and 4b of the thin lead wire 4 are spaced apart on both sides of the electrode 3. This is thought to be due to the fact that the main current path from the P type region 1a, the N + type region 1b, and the electrode 3 to the thin lead wire 4 is divided into left and right sides, and the current density in each is reduced. In particular, in this embodiment, the thin lead wire 4 is stretched diagonally across the electrode 3, which is advantageous because the distance L2 between the first connecting portion 4a and the second connecting portion 4b can be increased. Further, since the first connecting portion 1a and the second connecting portion 1b are in a straight line including the lead portion therebetween, stitch bonding can be performed satisfactorily.
【0010】0010
本考案は上述の実施例に限定されるものでなく、例えば次の変形が可能なもの である。 The present invention is not limited to the above-mentioned embodiments, but can be modified as follows, for example. It is.
【0011】 電極3の面積が大きい場合には電極3の辺に平行にボンディング領域9を設け ることができる。[0011] If the area of the electrode 3 is large, a bonding area 9 is provided parallel to the side of the electrode 3. can be done.
【0012】 電極3の面積が大きい時には、L2 をL1 及びL3 よりも大きくして電流集中 を更に緩和することができる。0012 When the area of electrode 3 is large, make L2 larger than L1 and L3 to concentrate the current. can be further relaxed.
【0013】 電極3は第1の金属膜6を肉厚に形成して、第2の金属膜7を省いた構成にす ることもできる。また第2の金属膜7を絶縁膜2の上側まで延在させて第1の金 属膜6の上面を完全に被覆するようにすることもできる。しかしながら、実際の 半導体装置では、この電極3の周囲にEQR(等電位リング)や他の電極の金属 層が形成されるので、これとの分離がエッチングによって良好に行えるよう、電 極3を二層以上とする。この場合、下側にエッチングが容易な相対的に薄い金属 膜を形成し、上側に電流容量の増大に寄与する相対的に厚い金属膜を形成する。[0013] The electrode 3 has a structure in which the first metal film 6 is formed thickly and the second metal film 7 is omitted. You can also Further, the second metal film 7 is extended to the upper side of the insulating film 2, and the first metal film 7 is It is also possible to completely cover the upper surface of the metal film 6. However, the actual In a semiconductor device, an EQR (equipotential ring) or other electrode metal is placed around this electrode 3. Since a layer is formed, the electric current is Pole 3 has two or more layers. In this case, a relatively thin metal on the underside that is easy to etch. A relatively thick metal film that contributes to an increase in current capacity is formed on the upper side.
【0014】[0014]
以上のように、本考案の半導体装置によれば電流容量が増大する。 As described above, according to the semiconductor device of the present invention, the current capacity increases.
【図1】本考案の実施例に係わる半導体装置の一部を示
すための図2の1−1線に相当する部分の断面図であ
る。FIG. 1 is a sectional view of a portion corresponding to line 1-1 in FIG. 2, showing a part of a semiconductor device according to an embodiment of the present invention.
【図2】図1の一部を示す平面図である。FIG. 2 is a plan view showing a part of FIG. 1;
1 半導体基板 2 絶縁膜 3 電極 4 リード細線 4a 第1の接続部 4b 第2の接続部 1 Semiconductor substrate 2 Insulating film 3 electrode 4 Thin lead wire 4a First connection 4b Second connection part
Claims (1)
形成された電極とを有し、同一のリード細線が前記電極
に対して互いに離間した2箇所以上で接続されているこ
とを特徴とする半導体装置。1. A semiconductor device comprising a semiconductor region and an electrode formed on a main surface of the semiconductor region, wherein the same thin lead wire is connected to the electrode at two or more locations spaced apart from each other. semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1991003721U JP2525558Y2 (en) | 1991-01-11 | 1991-01-11 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1991003721U JP2525558Y2 (en) | 1991-01-11 | 1991-01-11 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04103649U true JPH04103649U (en) | 1992-09-07 |
| JP2525558Y2 JP2525558Y2 (en) | 1997-02-12 |
Family
ID=31732900
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1991003721U Expired - Lifetime JP2525558Y2 (en) | 1991-01-11 | 1991-01-11 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2525558Y2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009283965A (en) * | 2009-07-23 | 2009-12-03 | Suzuka Fuji Xerox Co Ltd | Semiconductor device and wire bonding method |
| JP2012195459A (en) * | 2011-03-16 | 2012-10-11 | Sharp Corp | Wire bonding method and semiconductor device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5698859A (en) * | 1980-01-07 | 1981-08-08 | Mitsubishi Electric Corp | Solid-state electronic device |
| JPS5720149U (en) * | 1980-07-09 | 1982-02-02 | ||
| JPS648650A (en) * | 1987-06-30 | 1989-01-12 | Mitsubishi Electric Corp | Semiconductor lead frame |
| JPH02215137A (en) * | 1989-02-16 | 1990-08-28 | Sanyo Electric Co Ltd | High frequency semiconductor device |
-
1991
- 1991-01-11 JP JP1991003721U patent/JP2525558Y2/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5698859A (en) * | 1980-01-07 | 1981-08-08 | Mitsubishi Electric Corp | Solid-state electronic device |
| JPS5720149U (en) * | 1980-07-09 | 1982-02-02 | ||
| JPS648650A (en) * | 1987-06-30 | 1989-01-12 | Mitsubishi Electric Corp | Semiconductor lead frame |
| JPH02215137A (en) * | 1989-02-16 | 1990-08-28 | Sanyo Electric Co Ltd | High frequency semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009283965A (en) * | 2009-07-23 | 2009-12-03 | Suzuka Fuji Xerox Co Ltd | Semiconductor device and wire bonding method |
| JP2012195459A (en) * | 2011-03-16 | 2012-10-11 | Sharp Corp | Wire bonding method and semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2525558Y2 (en) | 1997-02-12 |
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