JPH0410422U - - Google Patents
Info
- Publication number
- JPH0410422U JPH0410422U JP5040690U JP5040690U JPH0410422U JP H0410422 U JPH0410422 U JP H0410422U JP 5040690 U JP5040690 U JP 5040690U JP 5040690 U JP5040690 U JP 5040690U JP H0410422 U JPH0410422 U JP H0410422U
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- circuit
- components
- signals
- guided
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 9
Landscapes
- Amplifiers (AREA)
Description
第１図ないし第３図に本考案実施例での回路配
線図を示し、第１図は反転増幅器回路配線図、第
２図は非反転増幅器回路配線図を構成した図、第
３図は本考案におけるパターン構造の略図、第４
図は本考案の回路基板パターンレイアウト構造図
、第５図は部品を載せて反転増幅回路を構成した
図、第６図は部品を載せて非反転増幅回路を構成
した図である。
１……グランドパターン、２……ＳＩＧパター
ン、３……−ＩＮパターン、４……＋ＩＮパター
ン、７……ジヤンパーチツプ、１２……オペアン
プ。
Figures 1 to 3 show circuit wiring diagrams in an embodiment of the present invention. Figure 1 is an inverting amplifier circuit wiring diagram, Figure 2 is a diagram configuring a non-inverting amplifier circuit wiring diagram, and Figure 3 is a diagram of the present invention. Schematic diagram of pattern structure in invention, Part 4
5 is a diagram showing the circuit board pattern layout structure of the present invention, FIG. 5 is a diagram showing an inverting amplifier circuit configured by mounting components, and FIG. 6 is a diagram configuring a non-inverting amplifier circuit by mounting components. 1... Ground pattern, 2... SIG pattern, 3... -IN pattern, 4... +IN pattern, 7... Jumper chip, 12... operational amplifier.
Claims (1)
から出力するように構成された回路基板のパター
ンレイアウト構造において、回路構成部品からの
信号が導かれてくるＳＩＧパターンと、オペアン
プのマイナス入力に導かれるマイナスＩＮパター
ンと、回路のグランドに導かれるグランドパター
ンとが、チツプ部品で接続可能な範囲に配設した
事を特徴とする回路基板のパターンレイアウト構
造。 In the pattern layout structure of a circuit board configured to output signals from circuit components through an amplifier circuit, there is a SIG pattern to which the signals from the circuit components are guided, and a negative pattern to which the signals from the circuit components are guided to the negative input of the operational amplifier. A pattern layout structure of a circuit board, characterized in that an IN pattern and a ground pattern led to the ground of the circuit are arranged in a range where they can be connected with chip components.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5040690U JPH0410422U (en) | 1990-05-15 | 1990-05-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5040690U JPH0410422U (en) | 1990-05-15 | 1990-05-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0410422U true JPH0410422U (en) | 1992-01-29 |
Family
ID=31568923
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5040690U Pending JPH0410422U (en) | 1990-05-15 | 1990-05-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0410422U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5595525U (en) * | 1978-12-25 | 1980-07-02 |
-
1990
- 1990-05-15 JP JP5040690U patent/JPH0410422U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5595525U (en) * | 1978-12-25 | 1980-07-02 |
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