JPH04105146A - Automatic setting system for extension memory bank - Google Patents

Abstract

PURPOSE:To unnecessitate the manual setting of the bank address of a memory board by securing the cascade connection among plural extension memory boards with use of a bank address setting grant signal. CONSTITUTION:Two registers 5 and 6 are initialized at initialization of a system and can be set by the software. One of both registers 5 and 6 sets a memory bank address of a board and generates a signal showing a fact that a memory provided on the board is selected via a comparator 7 which compares the set bank address and the address supplied from a CPU. The other register produces a bank address setting grant signal to the other memory board and secures the cascade connection among plural extension memory boards with use of the setting grant signal. As a result, the bank addresses of plural memory boards can be automatically set by the software. Thus the manual setting operations can be unnecessitated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to memory management of information processing devices, and in particular, to setting the bank address of a memory board in a computer system to which a plurality of additional memory boards are connected. Regarding the method of

[Conventional technology]

Information processing devices such as personal computers are designed to allow connection of multiple input/output expansion boards and additional memory boards in order to increase the versatility of the computer system.

When connecting an additional memory board among these function expansion boards, it is necessary to set the bank address (a fixed area on the computer system's memory map) of the additional memory board for the system. be.

Conventionally, this type of setting has been carried out by providing an arbitrarily settable switch on the memory board to be added, and by manually setting this switch, the address to be used by each board is determined.

[Problem to be solved by the invention]

As mentioned above, with the conventional bank address setting method, it is necessary to manually set the switches on the memory board when expanding the memory board, and a manual or other instruction manual is required for the system user to make the settings. In addition, there is a possibility that incorrect settings may be made due to human error during setting, which may lead to malfunctions, damage to the memory or board, etc., which is a drawback.

[Means to try to solve the problem]

The automatic expansion memory bank setting method of the present invention has two registers that are initialized at system initialization and can be set by software in an expansion memory board used in a computer system, and one of the two registers is , set the memory bank address for that board,
A comparator that compares the set bank address with the address supplied by the CPU generates a signal indicating that the memory on the board is selected when memory is accessed, and the other register It has a function of generating a bank address setting permission signal for a bank address and using this setting permission signal to connect a plurality of expansion memory boards in a cascade.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram for explaining an automatic expansion memory bank setting method according to an embodiment of the present invention, FIG. 2 is a diagram showing an example of a memory map according to this embodiment, and FIG. FIG. 3 is a diagram showing an example of cascade connection of memory ports.

In FIG. 1, the present embodiment includes a decoder 1, OR gates 2, 3, AND gate 4, NO, Lujistor 5, No.
It is composed of a register 6 and a comparator 7.

Decoder 1 has No. 2 register 5 and No. 2 register 6.
Data write permission signals ■ and ■ are generated from the address ■ supplied by CPtJ and the signal CPUENBO ■ indicating that the CPU is operating. Also, No. 2
The operation permission of decoder 1 is controlled by the output signal ■ (signal ■) of register 6, and at the time of initialization (signal ■ is
”), and when “1n” is written to the No. 2 register 6 (when the signal ■ is 01”), it is disabled.

OR gates 2 and 3 connect the CPU to other input/output devices (Il
o) Write command signal l0WO [phase] given to
Masked with the write permission signals ■ and ■ mentioned above, and when selected by the decoder (write permission signals ■ and ■ are “0”)
2) is supplied to the No. register 5 and the No. 2 register 6 as a tarok input.

AND gate 4 outputs signal I■ and reset command signal RES.
Generate a reset signal (■) for the No, Lujistar 5, and NO32 registers 6 from ETO@.

No, Lujistar 5 sets the bank address, No,
2 register 6 generates a signal ■ which is a decoder operation enable signal and a setting permission signal for the next memory board.

The comparator 7 compares the value ■ written in the register 5 with the upper bits indicating the bank address of the address ■ supplied by the CPU, and sends a memory select signal indicating that the memory on the board has been selected. ■Generate.

The input signal wire is connected to the output signal H of another board (the previous board in terms of memory setting order), as in the example of cascade connection of memory boards in FIG.

On boards other than memory boards, these signals are connected through.

In Figure 3, the output signal ■ of the No. 1 memory board is connected through a board other than the memory board, and the No. 12
It is the input signal for the memory board.

Next, its operation will be explained with reference to FIGS. 2 and 3.

In the memory map system shown in FIG. 2, assume that the bank address is set for an area of 100OOOH~ for the additional memory, with one memory board = IMB (H represents a hexadecimal number).

These memory areas have addresses 23 to 20 as shown at the bottom of Figure 2, the first one is 0001, the second one is 00.
It is expressed by setting it to 10.

Therefore, the first operation of this circuit is to write this data into registers on the board so that they correspond to the respective addresses. In the case of the first board, input signal 1 is given as a fixed value of "1" from the main system, and can be set in the register on the board at any time.

The value written in the register is compared with the upper address at the time of memory access by the comparator 7, and if the value matches the accessed address range, the memory select signal becomes active and memory access on the board becomes possible.

The second operation is to set data "1" to the No. 2 register 6, activate the setting permission signal (signal ■) for other memory boards, and disable the operation enable signal to the decoder. do.

This prevents a problem in which when multiple memory boards with the same circuit are mounted at the same time and settings are made using the same I10 port address (same decoder circuit), their settings overlap.

As a result, even if data is set to the next memory board, the contents of the registers on the own board do not change.

Next, these input signals ■ and output signals ■ are cascaded (connected in series) as shown in the example of cascade connection of memory boards in Fig. By writing to the register, bank addresses can be set without duplication.

〔Effect of the invention〕

As explained above, according to the present invention, by having both a memory bank address setting circuit having a register that can be set by a program and an I10 decoding circuit, and connecting a plurality of identical memory boards in a cascade,
It is now possible to automatically set the bank addresses of multiple memory boards using software without manual intervention, which eliminates the need for manual intervention and reduces human error. There is.

[Brief explanation of drawings]

FIG. 1 is a block diagram for explaining an automatic expansion memory bank setting method according to an embodiment of the present invention, FIG. 2 is a diagram showing an example of a memory map according to this embodiment, and FIG. FIG. 3 is a diagram showing an example of cascade connection of memory boards. 1... Decoder, 2, 3... OR gate, 4...
AND gate, 5-No, Lujistor, 6-No, 2 register, 7... comparator.

Claims (1)

[Claims] An expansion memory board used in a computer system has two registers that are initialized when the system is initialized and can be set by software, and one of the two registers is the register of the board. A comparator that sets a memory bank address and compares the set bank address with the address supplied by the CPU generates a signal indicating that the memory on the board is selected during memory access, and selects the other one. An automatic expansion memory bank setting method characterized in that the register has a function of generating a bank address setting permission signal for other memory boards and using this setting permission signal to connect a plurality of expansion memory boards in a cascade.