JPH0410540U - - Google Patents

Info

Publication number
JPH0410540U
JPH0410540U JP5181790U JP5181790U JPH0410540U JP H0410540 U JPH0410540 U JP H0410540U JP 5181790 U JP5181790 U JP 5181790U JP 5181790 U JP5181790 U JP 5181790U JP H0410540 U JPH0410540 U JP H0410540U
Authority
JP
Japan
Prior art keywords
signal line
surge absorption
absorption circuit
accessory device
grounded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5181790U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP5181790U priority Critical patent/JPH0410540U/ja
Publication of JPH0410540U publication Critical patent/JPH0410540U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Emergency Protection Circuit Devices (AREA)
  • Thermistors And Varistors (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図ないし第4図は本考案の実施例に係り、
第1図はサージ吸収回路の基本構成を示す電気回
路図であり、第2図ないし第4図はその変形例で
ある。また、第5図は、従来例に係るサージ吸収
回路の構成を示す電気回路図である。 図における符号1は付属機器、2は本体機器、
3は信号線路、4は抵抗素子、10は容量性バリ
スタ素子である。なお、図中の同一符号は、互い
に同一もしくは相当する部品、部分を示している
1 to 4 relate to embodiments of the present invention,
FIG. 1 is an electric circuit diagram showing the basic configuration of a surge absorption circuit, and FIGS. 2 to 4 are variations thereof. Moreover, FIG. 5 is an electric circuit diagram showing the configuration of a surge absorption circuit according to a conventional example. In the figure, numeral 1 is attached equipment, 2 is main equipment,
3 is a signal line, 4 is a resistive element, and 10 is a capacitive varistor element. Note that the same reference numerals in the drawings indicate parts and portions that are the same or correspond to each other.

Claims (1)

【実用新案登録請求の範囲】 付属機器1と本体機器2とを連結する信号線路
3に接続されたサージ吸収回路であつて、 信号線路3中に挿入された抵抗素子4と、これ
よりも付属機器1側に接続して接地された容量性
バリスタ素子10とを含むことを特徴とするサー
ジ吸収回路。
[Claims for Utility Model Registration] A surge absorption circuit connected to a signal line 3 connecting an accessory device 1 and a main device 2, comprising a resistive element 4 inserted into the signal line 3 and an accessory device from this. A surge absorption circuit comprising a capacitive varistor element 10 connected to a device 1 side and grounded.
JP5181790U 1990-05-17 1990-05-17 Pending JPH0410540U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5181790U JPH0410540U (en) 1990-05-17 1990-05-17

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5181790U JPH0410540U (en) 1990-05-17 1990-05-17

Publications (1)

Publication Number Publication Date
JPH0410540U true JPH0410540U (en) 1992-01-29

Family

ID=31571583

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5181790U Pending JPH0410540U (en) 1990-05-17 1990-05-17

Country Status (1)

Country Link
JP (1) JPH0410540U (en)

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