JPH0410543A - Formation of bump electrode of semiconductor device - Google Patents

Formation of bump electrode of semiconductor device

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Publication number
JPH0410543A
JPH0410543A JP11019090A JP11019090A JPH0410543A JP H0410543 A JPH0410543 A JP H0410543A JP 11019090 A JP11019090 A JP 11019090A JP 11019090 A JP11019090 A JP 11019090A JP H0410543 A JPH0410543 A JP H0410543A
Authority
JP
Japan
Prior art keywords
bump
electrode
resist film
resist
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11019090A
Other languages
Japanese (ja)
Inventor
Yutaka Okuaki
奥秋 裕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP11019090A priority Critical patent/JPH0410543A/en
Publication of JPH0410543A publication Critical patent/JPH0410543A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To contrive to prevent a metal from flowing out to the side of an inner lead or the corner part of each semiconductor element by a method wherein each one part of resist films over an electrode having an opening part is opened, the thicknesses of the resist films are formed in such a way that the outside resist film becomes thicker than the inside resist film and a bump electrode, whose bump top is formed in a state eccentric to the inside of each semiconductor element, is formed between the resist films. CONSTITUTION:A second resist film 27 is formed on the outside, the side of the so-called outer peripheral side, of an electrode 23 arranged and formed on the outer peripheral side of each unit element on a semiconductor substrate 21, a first resist film 26 only is formed on the inside, which is situated to the electrode, of each unit element formed on the main surface of the substrate 21 and the resist films are formed. After that, the electrode is put in a bump plating solution or is brought into contact to the bump plating solution, is made to conduct, a bump is formed, the resist films are removed and a bump 30 of a form is obtained. The form of the bump 30 is formed into a form that a bump top 32 is shifted on the inside of each semiconductor element on the substrate 21 to a center line 31 of the electrode 23. As the form of the bump is formed in such a way that the thicknesses of the resist films are thin on the inside of each unit element and are thick on the outside of each unit element, the reservoir part of a flowed-out metal is formed between an inner lead 40 and the bump 30.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、TAB (Tape Autos+ated
 Bondig)技術におけるバンプ電極の形状と、イ
ンナリード接続部の技術に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention is directed to TAB (Tape Autos+ated
The present invention relates to the shape of bump electrodes in the bonding technology and the technology of inner lead connection parts.

(従来の技術) 従来、このような分野の技術としては、例えば特公昭6
1−53853号に記載されるものがあった。
(Prior art) Conventionally, as a technology in this field, for example,
There was one described in No. 1-53853.

第2図はかかる従来の半導体装置のリード線と電極の接
続部近傍の断面図である。
FIG. 2 is a sectional view of the vicinity of the connection between the lead wire and the electrode of such a conventional semiconductor device.

この図に示すように、テープ状の樹脂フィルムに設けら
れた開孔に張り出されたリード線3には、接続すべき半
導体素子lの電極2の1引辺部近傍において凹部7が形
成されている。該凹部7はフォトレジストをマスクとす
る通常の選択エツチング法によって容易に形成される。
As shown in this figure, a recess 7 is formed in the lead wire 3 extending through the opening provided in the tape-shaped resin film near the first lead edge of the electrode 2 of the semiconductor element l to be connected. ing. The recess 7 is easily formed by a conventional selective etching method using a photoresist as a mask.

上記リード線3は更に錫メツキが施されるが、次工程以
降の熱処理による半田濡れ性への悪影響を防ぐために、
錫メツキ層3′を設ける。このリード線3は、例えば金
で作られた半導体素子電極2との間で金−錫の共晶合金
を形成して接続される。この時に接続時の熱によって溶
融或いは軟化した金属5が流れ出すが、表面張力により
リード線3の凹部7に9引され、半導体素子1とリード
線3との間を短絡される金属粒塊は生じなくなる。
The lead wire 3 is further tin-plated, but in order to prevent the heat treatment from the next process from having an adverse effect on the solder wettability.
A tin plating layer 3' is provided. The lead wire 3 is connected to the semiconductor element electrode 2 made of gold, for example, by forming a gold-tin eutectic alloy. At this time, the metal 5 that has been melted or softened by the heat generated during connection flows out, but is pulled into the recess 7 of the lead wire 3 due to surface tension, causing metal particles to be short-circuited between the semiconductor element 1 and the lead wire 3. It disappears.

第3図は従来のリード線の接続部近傍の凹部の他の配置
例を示したリード線と半導体素子の電極との接続部近傍
の断面図である。
FIG. 3 is a sectional view of the vicinity of the connection between the lead wire and the electrode of the semiconductor element, showing another example of the arrangement of recesses near the connection of the lead wire in the related art.

この図に示すように、半導体素子11の電極12の側辺
部近傍に凹部I7が形成され、該凹部17がIJ−ド線
13と素子電極12との接続時の熱により、溶融或いは
軟化して流れ出す金属15を表面張力により吸引する。
As shown in this figure, a recess I7 is formed near the side of the electrode 12 of the semiconductor element 11, and the recess 17 is melted or softened by the heat generated when the IJ-wire 13 and the element electrode 12 are connected. The metal 15 flowing out is attracted by surface tension.

(発明が解決しようとする課題) しかしながら、上記構成の半導体装置の電極とリード線
との接続方法では、インナリード先端部のエンチング加
工を行うことは、僅かに数十μmの厚さの材料であるの
で、先端部機械的強度の劣化、及びインナリード接続部
の対面及び上下面の位置出しにおいて、精度を要し、イ
ンナリード先端の凹部とハンプの位置合わせが難しいと
いう問題点があった。また、取扱時にインナリード先端
の変形等発生も増加し問題である。
(Problem to be Solved by the Invention) However, in the method for connecting the electrodes and lead wires of the semiconductor device with the above configuration, etching the tip of the inner lead is difficult to achieve with a material that is only several tens of μm thick. Therefore, there was a problem that the mechanical strength of the tip part deteriorated, and precision was required in positioning the facing and upper and lower surfaces of the inner lead connecting part, and it was difficult to align the concave part and the hump at the tip of the inner lead. Furthermore, the occurrence of deformation of the tip of the inner lead during handling increases, which is a problem.

また、接続時の問題として、バンプの頂上部は略平面化
されているので、ボンディングツールによってインナリ
ードを加熱すると、インナリード表面処理金属と、バン
プが溶接されるにあたり、溶融金属がバンプの外側(半
導体素子の外側に)コブとしてはみ出すという問題点が
あった。
Another problem when connecting is that the top of the bump is almost flat, so when the inner lead is heated with a bonding tool, the molten metal is welded to the surface-treated metal on the inner lead and the bump on the outside of the bump. There was a problem in that it protruded as a bump (outside the semiconductor element).

本発明は、以上述べた、接続時に流れ出しだ金錫共晶合
金等のインナリード支持部方向への流出を防止する凹部
を、インナリードの接続部側に形成することによって、
インナリードの機械的強度が劣化してしまうという問題
点を除去し、インナリードとハンプとの間に流出金属の
溜り部を形成するようにしたので、インナリード側又は
半導体素子コーナ部への金属の流出を防止することがで
きる。
According to the present invention, by forming a recess on the connection part side of the inner lead to prevent the gold-tin eutectic alloy, etc. that flows out at the time of connection from flowing out toward the inner lead support part, as described above,
This eliminates the problem of deterioration of the mechanical strength of the inner lead, and forms a pool of outflowing metal between the inner lead and the hump. It is possible to prevent the outflow of

(課題を解決するための手段) 本発明は、上記目的を達成するために、半導体素子の主
表面に形成された複数の電極部分に突起電極を形成する
半導体装置の突起電極の形成方法において、開口部を有
した前記電極の一部を開口したレジスト膜の厚さが前記
電極の内側レジスト膜厚と外側レジスト膜厚において、
外側レジスト膜が内側レジスト膜よりも厚くなるように
形成し、それらのレジスト膜間にバンブ頂部が半導体素
子の内側に偏心して形成される突起電極を形成するよう
にしたものである。
(Means for Solving the Problems) In order to achieve the above object, the present invention provides a method for forming protruding electrodes of a semiconductor device, in which protruding electrodes are formed on a plurality of electrode portions formed on the main surface of a semiconductor element. The thickness of the resist film with a part of the electrode having an opening is the inner resist film thickness and the outer resist film thickness of the electrode,
The outer resist film is formed to be thicker than the inner resist film, and a bump electrode is formed between these resist films so that the top of the bump is eccentrically formed inside the semiconductor element.

(作用) 本発明によれば、バンプの高さの頂部は、従来は電極の
略中央部にあったが、本発明によれば、上記したように
、バンプの頂部を電極の半導体素子中央側に偏心した位
置に形成するように、開口部を有した前記電極の一部を
開口したレジスト膜の厚さが前記電極の内側レジスト膜
厚と外側レジストWj!厚において外側レジスト膜が内
側レジスト膜よりも厚くなるように形成し、偏心された
位置にバンプを形成するようにしたので、インナリード
とバンプとの間に流出金属の溜り部が形成される。
(Function) According to the present invention, the top of the height of the bump was conventionally located approximately at the center of the electrode, but according to the present invention, as described above, the top of the bump is placed toward the center of the semiconductor element of the electrode. The thickness of a partially opened resist film of the electrode having an opening is equal to the inner resist film thickness of the electrode and the outer resist film Wj! Since the outer resist film is formed to be thicker than the inner resist film and the bumps are formed at eccentric positions, a pool of flowing metal is formed between the inner lead and the bumps.

従って、インナリード側又は半導体素子のコーナ部への
金属の流出を防止することができる。
Therefore, it is possible to prevent metal from flowing out to the inner lead side or the corner portion of the semiconductor element.

(実施例) 以下、本発明の実施例について図面を参照しながら詳細
に説明する。
(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

第1図は本発明の実施例を示す半導体装置の突起電極の
形成工程断面図である。
FIG. 1 is a sectional view showing a process of forming a protruding electrode of a semiconductor device according to an embodiment of the present invention.

まず、第1図(a)に示すように、シリコンからなる半
導体基板21上にはンリコン酸化膜(SiO□)リンガ
ラス膜PSG(Phospho 5ilicate G
lass) 、  シリコン窒化膜(S+3N4)等か
らなる絶縁膜22と、アルミニュウム、又はアルミニュ
ウム合金からなる電極23が蒸着等の方法で形成され、
エンチング等の方法によって局部的に半導体基板21の
主表面に形成されている。前記電極23上には接続金属
膜24とバリア金属膜25がそれぞれ形成され、接続金
属膜24はPt、 Ti、 Cr等の金属からなり、バ
リア金属膜25はCu、 Ni等からなる金属膜である
。これらの材料は限定されるものではない。また、それ
ぞれの各種用途、条件によって選定することができる。
First, as shown in FIG. 1(a), on a semiconductor substrate 21 made of silicon, a phosphorus oxide film (SiO
An insulating film 22 made of a silicon nitride film (S+3N4) or the like and an electrode 23 made of aluminum or an aluminum alloy are formed by a method such as vapor deposition.
It is locally formed on the main surface of the semiconductor substrate 21 by a method such as etching. A connection metal film 24 and a barrier metal film 25 are respectively formed on the electrode 23, the connection metal film 24 is made of a metal such as Pt, Ti, Cr, etc., and the barrier metal film 25 is a metal film made of Cu, Ni, etc. be. These materials are not limited. Further, it can be selected depending on various uses and conditions.

以上各種の部材からなる電極上に第1のレジスト膜26
を形成し、電極部28に通電し、バンプ30をメツキ成
長、形成させるが、本説明において電極部28には電極
23と同一部材等からなる導電膜を電極23表面及び半
導体基板21の主表面全面に形成し、バンプメツキ用の
電流を通電する前記導電膜は図示を省略した。
A first resist film 26 is formed on the electrode made of the various materials mentioned above.
is formed, the electrode section 28 is energized, and the bump 30 is plated and grown. The conductive film formed on the entire surface and through which a current for bump plating is passed is not shown.

更に、半導体基板21の主表面に回転塗布等の方法で第
1のレジスト膜26を形成し、現像、エツチング等の方
法で、レジスト開口部29を形成する。
Furthermore, a first resist film 26 is formed on the main surface of the semiconductor substrate 21 by a method such as spin coating, and a resist opening 29 is formed by a method such as development or etching.

その後、第2のレジスト膜27を形成し、第1のレジス
ト膜26と同一の方法によって現像又はエツチング等の
方法で、所定の形状の第2のレジスト膜27を形成する
。第1のレジスト膜26及び第2のレジスト膜27の形
成は、同一条件でもよいし、それぞれの方法によって、
露光、現像により開口部を形成する感光性レジスト、又
はマスキングしてエツチングによって、レジスト開口部
を形成する。
Thereafter, a second resist film 27 is formed, and the second resist film 27 having a predetermined shape is formed by the same method as the first resist film 26, such as development or etching. The first resist film 26 and the second resist film 27 may be formed under the same conditions, or by different methods.
Resist openings are formed by using a photosensitive resist that forms openings by exposure and development, or by masking and etching.

また、レジスト開口部29の形成は、第1のレジスト膜
26を形成した時に形成してもよいし、第2のレジスト
膜27を形成し、その後、2層のレジスト膜を同時に開
口処理するようにしてもよい。主として、−船釣に半導
体基板21の各単位素子の外周辺に配置形成された電極
23の外側、いわゆる外周部辺側に第2のレジスト#2
7を形成し、半導体基板21の主表面に形成された、各
単位素子の電極の内側に第1のレジスト膜26だけを形
成し、第1図に図示したレジスト膜を形成する。その後
、バンプメツキ液に投入又は接触させて導電させ、バン
プを形成し、レジストを除去し、第1図(b)に示す形
状のバンプ30を得る。このバンプ30の形状は、電極
23の中心線31に対してバンプ頂部32が半導体基板
21の各半導体素子の内側にずれる形状をなしている。
The resist openings 29 may be formed when the first resist film 26 is formed, or the second resist film 27 may be formed and then the two resist films may be opened at the same time. You can also do this. Mainly, a second resist #2 is applied on the outer side of the electrode 23 formed around the outer periphery of each unit element of the semiconductor substrate 21, that is, on the so-called outer periphery side.
7 is formed, and only the first resist film 26 is formed inside the electrode of each unit element formed on the main surface of the semiconductor substrate 21, thereby forming the resist film shown in FIG. Thereafter, it is placed in or brought into contact with a bump plating solution to conduct electricity to form a bump, and the resist is removed to obtain a bump 30 having the shape shown in FIG. 1(b). The shape of the bump 30 is such that the top portion 32 of the bump is shifted to the inside of each semiconductor element of the semiconductor substrate 21 with respect to the center line 31 of the electrode 23 .

ずれ量dは、第1図(c)に示すように、TAB実装技
術のインナリード接続に用いるインナリード40の太さ
、及び図示しないが、バンプとインナリードを接続(接
合)させるボンディングツールの大きさ、荷重、温度、
インナリード表面処理金属及びそれらの厚さと、バンプ
30の加熱時の溶融金属41の量等によって、種々のず
れ量dを調整し、最適値とする。バンプの高さも同様で
ある。
As shown in FIG. 1(c), the amount of deviation d depends on the thickness of the inner lead 40 used for inner lead connection in the TAB mounting technique and the bonding tool used to connect (bond) the bump and the inner lead (not shown). size, load, temperature,
Various deviation amounts d are adjusted to the optimum value depending on the inner lead surface treatment metals and their thicknesses, the amount of molten metal 41 when the bumps 30 are heated, and the like. The same applies to the height of the bump.

第1図(b)に示したバンプの形状は、レジスト膜の厚
さが各単位素子の内側が薄く、外側が厚く形成されてい
るので、バンプメッキ工程において、内側にはメツキ液
が良好に流れるので、メツキ成長が速く偏心した形状と
なる。従って、バンプメツキ時のメツキ液の流れ量、温
度等によっても種々の変形形状を得ることができる。
The shape of the bump shown in Figure 1(b) is such that the resist film is thinner on the inside of each unit element and thicker on the outside, so that the plating solution can be applied well to the inside during the bump plating process. Because it flows, plating grows quickly and takes on an eccentric shape. Therefore, various deformed shapes can be obtained depending on the flow rate, temperature, etc. of the plating liquid during bump plating.

なお、本発明は上記実施例に限定されるものではなく、
本発明の趣旨に基づき種々の変形が可能であり、それら
を本発明の範囲から排除するものではない。
Note that the present invention is not limited to the above embodiments,
Various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.

(発明の効果) 以上、詳細に説明したように、本発明によれば、バンプ
の頂部が電極の中心線に対して半導体素子の内側にずれ
るように形成したので、インナリードをバンプと接合し
た時に、溶融金属が流れ出してインナリード下部にコブ
が発生することがなくなる。
(Effects of the Invention) As described above in detail, according to the present invention, the top of the bump is formed so as to be shifted to the inside of the semiconductor element with respect to the center line of the electrode, so that the inner lead is bonded to the bump. This prevents the molten metal from flowing out and causing lumps at the bottom of the inner lead.

また、接合部(接点部)が内側になるので、溶融金属を
バンプとインナリードで保持する面積が広くなり、流れ
出し量が多くてもそれを有効に保持することができる。
Further, since the joint portion (contact portion) is located on the inside, the area for holding the molten metal between the bump and the inner lead becomes large, and even if there is a large amount of molten metal flowing out, it can be held effectively.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の実施例を示す半導体装置の突起電極の
形成工程断面図、第2図は従来の半導体装置のリード線
と電極の接続部近傍の断面図、第3図は従来のリード線
の接続部近傍の凹部の他の配置例を示したリード線と半
導体素子の電極との接続部近傍の断面図である。 21・・・半導体基板、22・・・絶縁膜、23・・・
電極、24・・・接続金属膜、25・・・バリア金属膜
、26・・・第1のレジスト膜、27・・・第2のレジ
スト膜、28・・・電極部、29・・・レジスト開口部
、30・・・バンプ、31・・・電極の中心線、32・
・・バンプ頂部、40・・・インナリード、41・・・
溶融金属。 特許出願人 沖電気工業株式会社 代理人 弁理士  清 水  守(外1名)木を8例の
441(本y若!の突A≧儂1企n貴り友J孝呈を訂正
ルね第1図 年t15Dキ41暖乙リート柩惇ヒの士か段音pメμ学
tパmii第2図 第 図
FIG. 1 is a cross-sectional view of the process of forming protruding electrodes of a semiconductor device showing an embodiment of the present invention, FIG. 2 is a cross-sectional view of the vicinity of the connection between a lead wire and an electrode of a conventional semiconductor device, and FIG. 3 is a cross-sectional view of a conventional lead FIG. 7 is a cross-sectional view of the vicinity of the connection between the lead wire and the electrode of the semiconductor element, showing another example of the arrangement of recesses near the connection of the wire; 21... Semiconductor substrate, 22... Insulating film, 23...
Electrode, 24... Connection metal film, 25... Barrier metal film, 26... First resist film, 27... Second resist film, 28... Electrode portion, 29... Resist Opening, 30... Bump, 31... Center line of electrode, 32.
...Bump top, 40...Inner lead, 41...
molten metal. Patent Applicant Oki Electric Industry Co., Ltd. Agent Patent Attorney Mamoru Shimizu (1 other person) Revised 8 cases of 441 (Book y Waka!'s Project A ≧ My 1 Plan n Takashi Tomo J Takasei) Figure 1 Year t15D Ki 41 Dan Otsu Rit Hitsugi Junhi no Shika Danon p Memu Gakut Pamii Figure 2 Figure

Claims (1)

【特許請求の範囲】  半導体素子の主表面に形成された複数の電極部分に突
起電極を形成する半導体装置の突起電極の形成方法にお
いて、 開口部を有した前記電極の一部を開口したレジスト膜の
厚さが前記電極の内側レジスト膜厚と外側レジスト膜厚
において外側レジスト膜が内側レジスト膜よりも厚くな
るように形成し、それらのレジスト膜間にバンプ頂部が
半導体素子の内側に偏心して形成される突起電極を形成
する半導体装置の突起電極の形成方法。
[Scope of Claims] A method for forming a protruding electrode of a semiconductor device in which protruding electrodes are formed on a plurality of electrode portions formed on a main surface of a semiconductor element, comprising: a resist film in which a portion of the electrode having an opening is opened; is formed such that the outer resist film is thicker than the inner resist film between the inner resist film thickness and the outer resist film thickness of the electrode, and the bump top is eccentrically formed inside the semiconductor element between these resist films. A method for forming a protruding electrode of a semiconductor device.
JP11019090A 1990-04-27 1990-04-27 Formation of bump electrode of semiconductor device Pending JPH0410543A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11019090A JPH0410543A (en) 1990-04-27 1990-04-27 Formation of bump electrode of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11019090A JPH0410543A (en) 1990-04-27 1990-04-27 Formation of bump electrode of semiconductor device

Publications (1)

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JPH0410543A true JPH0410543A (en) 1992-01-14

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10017746A1 (en) * 2000-04-10 2001-10-18 Infineon Technologies Ag Electronic component with microscopic contact surfaces and process for its manufacture
US6555849B1 (en) 1998-05-12 2003-04-29 Infineon Technologies Ag Deactivatable thyristor
JP2011129824A (en) * 2009-12-21 2011-06-30 Fujitsu Ltd Method of manufacturing electronic device, and device for manufacturing electronic component

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6555849B1 (en) 1998-05-12 2003-04-29 Infineon Technologies Ag Deactivatable thyristor
DE10017746A1 (en) * 2000-04-10 2001-10-18 Infineon Technologies Ag Electronic component with microscopic contact surfaces and process for its manufacture
US6946725B2 (en) 2000-04-10 2005-09-20 Infineon Technologies Ag Electronic device having microscopically small contact areas and methods for producing the electronic device
DE10017746B4 (en) * 2000-04-10 2005-10-13 Infineon Technologies Ag Method for producing an electronic component with microscopically small contact surfaces
JP2011129824A (en) * 2009-12-21 2011-06-30 Fujitsu Ltd Method of manufacturing electronic device, and device for manufacturing electronic component

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