JPH04105446A - Data transmitter-receiver - Google Patents
Data transmitter-receiverInfo
- Publication number
- JPH04105446A JPH04105446A JP2223920A JP22392090A JPH04105446A JP H04105446 A JPH04105446 A JP H04105446A JP 2223920 A JP2223920 A JP 2223920A JP 22392090 A JP22392090 A JP 22392090A JP H04105446 A JPH04105446 A JP H04105446A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- data
- data signal
- received
- detection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims abstract description 59
- 230000001934 delay Effects 0.000 claims description 4
- 230000003111 delayed effect Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 1
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Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、データ伝送のデータ送受信装置に利用する。[Detailed description of the invention] [Industrial application field] INDUSTRIAL APPLICATION This invention is utilized for the data transmission/reception apparatus of data transmission.
特に、疑似キャリア方式によりデータを送受信するデー
タ送受信装置に関するものである。In particular, the present invention relates to a data transmitting/receiving device that transmits and receives data using a pseudo carrier method.
本発明のデータ送受信装置において、
データ信号終了後の連続アイドルパタン検出ビット数と
同じピント数分遅延された受信信号に基づきデータ開始
パタンの検出を行い、遅延されない受信信号に基づきデ
ータ信号終了後の連続アイドルパタンの検出を行うこと
により、
受信データ信号中に受信データと見分けのつかない余分
なビットが存在することがないようにしたものである。In the data transmitting/receiving device of the present invention, the data start pattern is detected based on the received signal delayed by the same number of focus points as the continuous idle pattern detection bit number after the data signal ends, and the data start pattern is detected after the data signal ends based on the undelayed received signal. By detecting continuous idle patterns, it is possible to prevent the presence of extra bits in the received data signal that are indistinguishable from the received data.
第３図は従来例のデータ送受信装置のブロック構成図で
ある。第４図は従来例のデータ送受信装置の各部分の信
号波形のタイミングチャートである。FIG. 3 is a block diagram of a conventional data transmitting/receiving device. FIG. 4 is a timing chart of signal waveforms of various parts of a conventional data transmitting/receiving device.
従来、疑似キャリア方式によるデータ送受信装置は、第
３図に示すように、受信信号１１を人力するシフトレジ
スタ回路５と、シフトレジスタ回路５の出力から規定デ
ータ信号開始終了パタンを検出するデータ信号開始終了
検出回路３と、受信信号１１を人力しデータ信号開始終
了パタン検出回路３出力により制御され受信信号１１の
データ信号である受信データ信号１４を端末装置に出力
する制御回路４を備える。Conventionally, as shown in FIG. 3, a data transmitting/receiving device using a pseudo carrier system includes a shift register circuit 5 that manually inputs a received signal 11, and a data signal start/receiver circuit that detects a specified data signal start/end pattern from the output of the shift register circuit 5. The control circuit 4 includes an end detection circuit 3 and a control circuit 4 which manually inputs the received signal 11 and outputs a received data signal 14, which is a data signal of the received signal 11, to a terminal device under the control of the output of the data signal start/end pattern detection circuit 3.
第４図において、疑似キャリア方式では、対向データ送
信装置は、送信データ （受信信号１１）がデータ信号
でないときにはある所定アイドルレノくタンＡを送信す
る。データ信号を送信するときにはその前に規定データ
信号開始ノくタンＢのあらかじめ定められたビット数Ｘ
を送信してからデータ信号を送信し、データ信号送信が
終了すると再び所定アイドルパタンＡを送信している。In FIG. 4, in the pseudo carrier method, the opposing data transmitting device transmits a certain predetermined idle signal A when the transmitted data (received signal 11) is not a data signal. Before transmitting a data signal, a predetermined number of bits
After transmitting the data signal, the data signal is transmitted, and when the data signal transmission is completed, the predetermined idle pattern A is transmitted again.
シフトレジスタ回路５は、上記あらかじめ定約られたビ
ット数Ｙのシフトレジスタ回路である。The shift register circuit 5 is a shift register circuit having the predetermined number Y of bits.
データ信号開始終了パタン検出回路３は、シフトレジス
タ回路５の各段出力を監視し、受信信号１１中に規定デ
ータ信号開始パタンＢのあらかじめ定於られたビット数
Ｋを検出するとただちにデータ検出信号１３を「オン」
とする。また、データ信号が終了した後の所定アイドル
パタンＡをあらかじめ定められたビット数Ｋを検出する
とただちにデータ検出信号１３を「オフ」とする。The data signal start/end pattern detection circuit 3 monitors the output of each stage of the shift register circuit 5, and as soon as it detects a predetermined number of bits K of the specified data signal start pattern B in the received signal 11, the data signal start/end pattern detection circuit 3 outputs a data detection signal 13. "on"
shall be. Further, as soon as a predetermined number of bits K of the predetermined idle pattern A after the end of the data signal is detected, the data detection signal 13 is turned off.
制御回路４は、データ検出信号１３が「オン」の場合に
は、受信信号１１を受信データ信号１４とし、また「オ
フ」の場合には、マークにホールドした信号を受信デー
タ１４として出力する。When the data detection signal 13 is "on", the control circuit 4 outputs the received signal 11 as the received data signal 14, and when it is "off", the control circuit 4 outputs the signal held in the mark as the received data 14.
しかし、このような従来例のデータ送受信装置では、デ
ータ終了後の所定アイドルパタンＡを検知する期間はデ
ータ信号開始終了パタン検出回路３のデータ検出信号１
３が「オン」のままであるためにこの期間の所定アイド
ルパタンＡは受信データと見分けがつかないので受信デ
ータ１４として出力される欠点があった。However, in such a conventional data transmitting/receiving device, the period for detecting the predetermined idle pattern A after the end of data is the data detection signal 1 of the data signal start/end pattern detection circuit 3.
3 remains "on", the predetermined idle pattern A during this period is indistinguishable from the received data, and has the disadvantage that it is output as the received data 14.
本発明は上記の欠点を解決するもので、受信データ信号
中に受信データの見分けのつかない余分なビットが存在
することがないデータ送受信装置を提供することを目的
とする。The present invention solves the above-mentioned drawbacks and aims to provide a data transmitting/receiving device in which no indistinguishable extra bits of the received data are present in the received data signal.
本発明は、対向データ送信装置から受信した受信信号の
規定データ開始パタンを検出してデータ検出信号を「オ
ン」にし、この受信信号の所定アイドルパタンを検出し
てこのデータ検出信号を「オフ」にするデータ信号開始
終了検出回路と、上記データ検出信号が「オン」のとき
に上記受信信号を受信データ信号として端子装置に出力
し、上記データ検出信号が「オフ」のときにマークにホ
ールドした信号を受信データ信号として出力する制御回
路とを備えたデータ送受信装置において、上記受信信号
を受信して上記データ信号開始パタン検出用シフトレジ
スタ回路に与えるアイドルパタン検出用シフトレジスタ
回路と、上記アイドルパタン検出用ソフトレジスタ回路
の出力信号をデータ信号終了後の連続所定アイドルパタ
ン検出ビット数と同じビット数分遅延して上記データ信
号開始終了検出回路に与えるデータ信号開始パタン検出
用シフトレジスタ回路とを備えたことを特徴とする。The present invention detects a prescribed data start pattern of a received signal received from an opposing data transmitting device and turns the data detection signal "on," and detects a prescribed idle pattern of this received signal and turns the data detection signal "off." a data signal start/end detection circuit that outputs the received signal as a received data signal to a terminal device when the data detection signal is "on", and holds it at the mark when the data detection signal is "off". A data transmitting/receiving device comprising: a control circuit for outputting a signal as a received data signal; and a shift register circuit for detecting a data signal start pattern, which delays the output signal of the detection soft register circuit by a number of bits equal to the number of successive predetermined idle pattern detection bits after the end of the data signal and supplies it to the data signal start/end detection circuit. It is characterized by:
また、上記受信信号は、データ信号と、データ信号でな
いときに送信する所定アイドルパタンと、データ信号の
直前に付加される規定データ信号開始パタンとで構成さ
れることができる。Further, the received signal can be composed of a data signal, a predetermined idle pattern that is transmitted when the signal is not a data signal, and a predetermined data signal start pattern that is added immediately before the data signal.
アイドルパタン検出用シフトレジスタ回路は受信信号を
受信してデータ信号開始パタン検出用シフトレジスタ回
路に与える。データ信号開始パタン検出用シフトレジス
タ回路はアイドルパタン検出用シフトレジスタ回路の出
力信号をデータ信号終了後の連続所定アイドルパタン検
出ビット数と同じビット数分遅延してデータ信号開始終
了検出回路に与える。The idle pattern detection shift register circuit receives the received signal and supplies it to the data signal start pattern detection shift register circuit. The data signal start pattern detection shift register circuit delays the output signal of the idle pattern detection shift register circuit by the same number of bits as the number of continuous predetermined idle pattern detection bits after the end of the data signal, and supplies it to the data signal start and end detection circuit.
また、受信信号は、データ信号と、データ信号でないと
きに送信する所定アイドルパタンと、データ信号の直前
に付加される規定データ信号開始パタンとで構成される
。Further, the received signal is composed of a data signal, a predetermined idle pattern that is transmitted when the signal is not a data signal, and a predetermined data signal start pattern that is added immediately before the data signal.
以上により受信データ中に受信データと見分けのつかな
い余分なビットが存在することがないようにできる。As described above, it is possible to prevent the presence of extra bits in the received data that are indistinguishable from the received data.
本発明の実施例について図面を参照して説明する。第１
図は本発明のデータ送受信装置のブロック構成図である
。第１図において、データ送受信装置は、対向データ送
信装置から受信した受信信号１１の規定データ開始パタ
ンＢを検出してデータ検出信号１３を「オン、・にし、
この受信信号１１の所定アイドルパタンＡを検出してこ
のデータ検出信号１３を「オフＪにするデータ信号開始
終了検出回路３と、データ検出信号１３が「オン」のと
きに受信信号１１を受信データ信号１４として端末装置
に出力し、データ検出信号１３が「オフ」のときにでり
にホールドした信号を受信データ信号１４として出力す
る制御回路４とを備える。Embodiments of the present invention will be described with reference to the drawings. 1st
The figure is a block diagram of a data transmitting/receiving device according to the present invention. In FIG. 1, the data transmitting/receiving device detects a prescribed data start pattern B of the reception signal 11 received from the opposite data transmitting device, turns on the data detection signal 13,
A data signal start/end detection circuit 3 detects a predetermined idle pattern A of this received signal 11 and turns this data detection signal 13 off. The control circuit 4 outputs a signal 14 to the terminal device and outputs a signal held at the end when the data detection signal 13 is "off" as the received data signal 14.
ここで本発明の特徴とするところは、
受信信号１１を受信してデータ信号開始パタン検出用シ
フトレジスタ回路２に与えるアイドルパタン検出用シフ
トレジスタ回路１と、アイドルパタン検出用シフトレジ
スタ回路１の出力信号をデータ信号終了後の連続所定ア
イドルパタン検出ピント数と同じビット数分遅延してデ
ータ信号開始終了検出回路３に与えるデータ信号開始パ
タン検出用シフトレジスタ回路２とを備えたことにある
。Here, the features of the present invention are: an idle pattern detection shift register circuit 1 that receives a received signal 11 and supplies it to a data signal start pattern detection shift register circuit 2; and an output of the idle pattern detection shift register circuit 1. A shift register circuit 2 for detecting a data signal start pattern is provided, which delays the signal by the same number of bits as the number of continuous predetermined idle pattern detection focuses after the end of the data signal and supplies the signal to the data signal start/end detection circuit 3.
また、受信信号１１は、データ信号と、データ信号でな
いときに送信する所定アイドルパタン八と、データ信号
の直前に付加される規定データ信号開始パタンＢとで構
成される。The received signal 11 is composed of a data signal, a predetermined idle pattern 8 that is transmitted when the signal is not a data signal, and a predetermined data signal start pattern B that is added immediately before the data signal.
このような構成のデータ送受信装置の動作について説明
する。第２図は本発明のデータ送受信装置の各部分の信
号波形のタイミングチャートである。第１図および第２
図において、受信信号１１は、データ信号でないときは
常時所定アイドルパタンＡで、データ信号が始まる直前
にあらかじめ定めたピッ）Ｘの規定データ開始パタンＢ
がきてデータ信号となる。データ信号が終了すると再び
所定アイドルパタンＡとなる（疑似キャリア方式）。The operation of the data transmitting/receiving device having such a configuration will be explained. FIG. 2 is a timing chart of signal waveforms of each part of the data transmitting/receiving device of the present invention. Figures 1 and 2
In the figure, the received signal 11 is always a predetermined idle pattern A when it is not a data signal, and a predetermined data start pattern B with a predetermined beep) X immediately before the data signal starts.
comes and becomes a data signal. When the data signal ends, it becomes the predetermined idle pattern A again (pseudo carrier method).
データ信号開始パタン検出用シフトレジスタ回路２は、
受信信号１１を遅延しくたとえばビット数Ｙ遅延する。The shift register circuit 2 for detecting a data signal start pattern is
The received signal 11 is delayed, for example, by Y bits.
）、遅延受信信号１２を出力する。データ信号開始パタ
ン検出用レジスタ回路２は、規定データ開始パタンＢの
ビット数Ｘと同ビット数のシフトレジスタ回路であり、
各段の出力をデータ信号開始終了検出回路３で監視され
ている。データ信号開始終了検出回路３は、遅延受信信
号１２中にビット数Ｘの規定データ開始パタンＢを検知
すると、ただちにデータ検出信号１３を「オン」にする
。), which outputs the delayed received signal 12. The data signal start pattern detection register circuit 2 is a shift register circuit with the same number of bits as the bit number X of the specified data start pattern B,
The output of each stage is monitored by a data signal start/end detection circuit 3. When the data signal start/end detection circuit 3 detects the specified data start pattern B having the number of bits X in the delayed reception signal 12, it immediately turns the data detection signal 13 "on".
また、データ信号開始終了検出回路３は、データ信号開
始パタン検出用シフトレジスタ回路２の各段の出力も監
視しており、受信信号１１中に連続した所定アイドルパ
タンＡのビット数Ｙを検出するとただちにデータ検出信
号１３を「オフ」とする。The data signal start/end detection circuit 3 also monitors the output of each stage of the shift register circuit 2 for data signal start pattern detection, and when it detects the number Y of consecutive predetermined idle patterns A in the received signal 11, The data detection signal 13 is immediately turned off.
制御回路４は、データ検出信号１３が「オン」の場合に
のみ遅延受信信号１２を受信データ信号１４として端末
装置に出力し、また「オフ」の場合には出力をマークに
ホールドして受信データ信号１４として出力する。した
がって、データ検出信号１３が「オン」のときに受信デ
ータ信号１４中にデータ信号と見分けのつかない余分な
ビットが存在することがない。The control circuit 4 outputs the delayed reception signal 12 as a reception data signal 14 to the terminal device only when the data detection signal 13 is "on", and when it is "off", it holds the output as a mark and outputs the reception data. Output as signal 14. Therefore, when the data detection signal 13 is "on", there will be no extra bits in the received data signal 14 that are indistinguishable from the data signal.
以上説明したように、本発明は、受信データ中に受信デ
ータと見分けのつかない余分なビットが存在することが
な（なる優れた効果がある。As described above, the present invention has an excellent effect of preventing the presence of extra bits in the received data that are indistinguishable from the received data.
第１図は本発明一実施例データ送受信装置のブロック構
成図。
第２図は本発明のデータ送受信装置の各部分の信号波形
のタイミングチャート。
第３図は従来例のデータ送受信装置のブロック構成図。
第４図は従来例のデータ送受信装置の各部分の信号波形
のタイミングチャート。
１・・・アイドルパタン検出用シフトレジスタ回路、２
・・・データ信号開始パタン検出用シフトレジスタ回路
、３・・・データ信号開始終了検出回路、４・・・制御
回路、１１・・・受信信号、１２・・・遅延受信信号、
１３・・・データ検出信号、１４・・・受信データ信号
、Ａ・・・所定アイドルパタン、Ｂ・・・規定データ開
始パタン。FIG. 1 is a block diagram of a data transmitting/receiving device according to an embodiment of the present invention. FIG. 2 is a timing chart of signal waveforms of each part of the data transmitting/receiving device of the present invention. FIG. 3 is a block diagram of a conventional data transmitting/receiving device. FIG. 4 is a timing chart of signal waveforms of various parts of a conventional data transmitting/receiving device. 1... Shift register circuit for idle pattern detection, 2
...Shift register circuit for detecting a data signal start pattern, 3.. Data signal start/end detection circuit, 4.. Control circuit, 11.. Reception signal, 12.. Delayed reception signal.
13... Data detection signal, 14... Received data signal, A... Predetermined idle pattern, B... Prescribed data start pattern.
Claims (1)
ータ開始パタンを検出してデータ検出信号を「オン」に
し、この受信信号の所定アイドルパタンを検出してこの
データ検出信号を「オフ」にするデータ信号開始終了検
出回路と、 上記データ検出信号が「オン」のときに上記受信信号を
受信データ信号として端子装置に出力し、上記データ検
出信号が「オフ」のときにマークにホールドした信号を
受信データ信号として出力する制御回路と を備えたデータ送受信装置において、 上記受信信号を受信して上記データ信号開始パタン検出
用シフトレジスタ回路に与えるアイドルパタン検出用シ
フトレジスタ回路と、 上記アイドルパタン検出用シフトレジスタ回路の出力信
号をデータ信号終了後の連続所定アイドルパタン検出ビ
ット数と同じビット数分遅延して上記データ信号開始終
了検出回路に与えるデータ信号開始パタン検出用シフト
レジスタ回路とを備えたことを特徴とするデータ送受信
装置。 ２、上記受信信号は、データ信号と、データ信号でない
ときに送信する所定アイドルパタンと、データ信号の直
前に付加される規定データ信号開始パタンとで構成され
た請求項１記載のデータ送受信装置。[Claims] 1. Detect a prescribed data start pattern of a received signal received from the opposing data transmitting device, turn on the data detection signal, detect a prescribed idle pattern of this received signal, and turn on the data detection signal. a data signal start/end detection circuit that turns OFF, and outputs the received signal to a terminal device as a received data signal when the data detection signal is OFF, and outputs the received signal to the terminal device as a received data signal when the data detection signal is OFF. A data transmitting/receiving device comprising: a control circuit for outputting a signal held in a mark as a received data signal; , a shift register for data signal start pattern detection that delays the output signal of the idle pattern detection shift register circuit by a number of bits equal to the number of successive predetermined idle pattern detection bits after the end of the data signal and supplies the output signal to the data signal start/end detection circuit; A data transmitting/receiving device characterized by comprising a circuit. 2. The data transmitting/receiving device according to claim 1, wherein the received signal is composed of a data signal, a predetermined idle pattern that is transmitted when the signal is not a data signal, and a predetermined data signal start pattern that is added immediately before the data signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2223920A JPH04105446A (en) | 1990-08-24 | 1990-08-24 | Data transmitter-receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2223920A JPH04105446A (en) | 1990-08-24 | 1990-08-24 | Data transmitter-receiver |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04105446A true JPH04105446A (en) | 1992-04-07 |
Family
ID=16805787
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2223920A Pending JPH04105446A (en) | 1990-08-24 | 1990-08-24 | Data transmitter-receiver |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04105446A (en) |
-
1990
- 1990-08-24 JP JP2223920A patent/JPH04105446A/en active Pending
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| JPS6276835A (en) | Transmission control method |