JPH0410560A - Hybrid integrated circuit - Google Patents
Hybrid integrated circuitInfo
- Publication number
- JPH0410560A JPH0410560A JP2113121A JP11312190A JPH0410560A JP H0410560 A JPH0410560 A JP H0410560A JP 2113121 A JP2113121 A JP 2113121A JP 11312190 A JP11312190 A JP 11312190A JP H0410560 A JPH0410560 A JP H0410560A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- hole
- substrate
- integrated circuit
- conductive sheet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
(イ)産業上の利用分野
本発明は混成集積回路に関し、特に書き込み消去可能な
データを有する樹脂封止型半導体素子を搭載した混成集
積回路に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a hybrid integrated circuit, and more particularly to a hybrid integrated circuit equipped with a resin-sealed semiconductor element having writable and erasable data.
(ロ)従来の技術
通常、混成集積回路は第5図に示す如く、混成集積回路
基板(21)上に複数の回路素子(22)が固着され、
回路素子(22)を密封封止するために樹脂性のケース
材(23)が混成集積回路基板(21〉に固着され一体
化されている。(B) Conventional technology Usually, as shown in FIG. 5, a hybrid integrated circuit has a plurality of circuit elements (22) fixed on a hybrid integrated circuit board (21).
A resin case material (23) is fixed and integrated with the hybrid integrated circuit board (21>) in order to hermetically seal the circuit element (22).
断る混成集積回路にEPROMあるいはマイ′コ〉′等
の所定のデータを書き込み、消去することかできる半導
体素子を固着実装する場合は第6図に示す如く、半導体
チップ(24〉を基板(21〉上にダイボンドしてケー
ス材(23)で封止する構造あるいは第7図に示す如く
3.半導体チップが樹脂封止きれた半導体装置(25)
を基板(21)上に半田付けしてケース材(23)で封
止する構造が一般的であった。When a semiconductor element such as an EPROM or micro-chip capable of writing and erasing predetermined data is fixedly mounted on a hybrid integrated circuit, the semiconductor chip (24) is mounted on a substrate (21) as shown in FIG. 3. Semiconductor device (25) in which the semiconductor chip is completely sealed with resin, as shown in Figure 7.
It was common to have a structure in which the capacitor was soldered onto a substrate (21) and sealed with a case material (23).
(ハ)発明が解決しようとする課題
斯るEFROMあるいはマイコン等の所定のデータを書
き込み、消去することができる半導体素子が内蔵される
混成集積回路では、ケース材が固着一体止されているた
めに素子のデータの変更があれば混成集積回路自体の交
換を行っていた。(c) Problems to be Solved by the Invention In hybrid integrated circuits such as EFROMs or microcomputers that have built-in semiconductor elements that can write and erase predetermined data, the case material is fixed and integral. If there was a change in element data, the hybrid integrated circuit itself had to be replaced.
その理由として半導体素子自体の交換が非常に困難であ
る。また、交換中に他の素子が破損する恐れがある。The reason for this is that it is extremely difficult to replace the semiconductor element itself. Furthermore, there is a risk that other elements may be damaged during replacement.
また、従来の混成集積回路構造で多品種少量生産を行う
場合には、EFROM等の半導体素子のデータが異なる
ために異種の製造ライン又は製造装置を必要とすると共
に製造期間が長くなり製造コストか高くなる問題がある
。In addition, when performing high-mix, low-volume production using conventional hybrid integrated circuit structures, different data on semiconductor devices such as EFROMs require different types of manufacturing lines or manufacturing equipment, and the manufacturing period becomes longer and manufacturing costs increase. The problem is that it gets expensive.
(幻課題を解決するだめの手段
本発明は上述した課題に鑑みて為されたものであり、集
積回路基板と前記基板上に形成きれた所望形状の導電路
と前記基板上の導電路と接続きれた複数の回路素子およ
び樹脂封止された半導体素子と前記基板と一体化される
ケース材とを具備し、前記ケース材の所定位置に孔を設
け、その孔で露出した前記基板上に導電性シートを配置
し、前記導電性シート上に前記半導体素子のみを搭載し
、前記ケース材の孔の周端辺と蓋体とを螺着させ前記半
導体素子を押圧接続したことを特徴とする。(Means for Solving the Phantom Problems) The present invention has been made in view of the above-mentioned problems, and includes an integrated circuit board, a conductive path of a desired shape formed on the board, and a connection with the conductive path on the board. A case material is provided that is integrated with the substrate and a plurality of circuit elements and resin-sealed semiconductor elements, and a hole is provided at a predetermined position of the case material, and a conductive material is formed on the substrate exposed through the hole. A conductive sheet is disposed, only the semiconductor element is mounted on the conductive sheet, and the semiconductor element is press-connected by screwing the peripheral edge of the hole of the case material to the lid.
(ホ)作用
この様に本発明に依れば、ケース材の所定位置に孔を形
成し、その孔で露出された基板上に導電性シートを配置
し、そのシート上に所定のプログラムデータを有する半
導体素子を搭載してケース材の孔の周端辺と蓋体とを螺
着させ半導体素子を押圧接続することにより、半導体素
子を半FB(′:iけすることなく導電路と接続するこ
とができる。(E) Function As described above, according to the present invention, a hole is formed at a predetermined position in the case material, a conductive sheet is placed on the substrate exposed through the hole, and predetermined program data is written on the sheet. The semiconductor element is mounted on the semi-FB (') by screwing the peripheral edge of the hole of the case material and the lid body and pressingly connecting the semiconductor element to the conductive path without cutting. be able to.
また、ケース材と蓋体との螺着によって押圧接続が行わ
れるために、上述した様に半田付レスになると共に半導
体素子の着脱を極めて容易に実現できる。Further, since the press connection is made by screwing the case material and the lid, there is no need to solder as described above, and the semiconductor element can be attached and detached very easily.
(へ)実施例
以下に第1図に示した実施例に基ついて本発明の混成集
積回路を詳細に説明する。(F) Embodiment The hybrid integrated circuit of the present invention will be explained in detail below based on the embodiment shown in FIG.
本発明の混成集積回路は第1図に示す如く、集積回路基
板(1)と、その基板<1)上に形成された所望形状の
導電路(2)と、その導電路(2)と接続された複数の
回路素子(3)と、基板(1)と一体止され所望位置に
孔(5)が設けられたケース材(4)と、孔(5)で露
出した基板(1)上に搭載きれた導電性レート(6)と
、導電性シート(6)上に載置された樹脂封止型の半導
体素子(7)とから構成される。As shown in FIG. 1, the hybrid integrated circuit of the present invention includes an integrated circuit substrate (1), a conductive path (2) of a desired shape formed on the substrate (<1), and a connection with the conductive path (2). A case material (4) that is integrally fixed to the substrate (1) and has a hole (5) at a desired position, and a plurality of circuit elements (3) that are It is composed of a fully mounted conductive plate (6) and a resin-sealed semiconductor element (7) placed on the conductive sheet (6).
集積回路基板(1)はセラミックスあるいは金属基板が
用いられ、本実施例では放熱性で優れた金属基板を用い
るものとする。基板(1)としてはアルミニウム基板を
用いるものとし、そのアルミニウム基板の表面には絶縁
とするために酸化アルミラム膜が形成されている。アル
ミニウム基板の他、鉄、ホーロー、ケイ素鋼板等の基板
を使用することも可能である。A ceramic or metal substrate is used as the integrated circuit board (1), and in this embodiment, a metal substrate with excellent heat dissipation properties is used. An aluminum substrate is used as the substrate (1), and an aluminum oxide lamb film is formed on the surface of the aluminum substrate for insulation. In addition to the aluminum substrate, it is also possible to use a substrate made of iron, enamel, silicon steel, or the like.
基板(1)上には絶縁樹脂薄層(図示しない)を介して
銅箔が貼着され、その銅箔を所望形状にエツチングして
所望形状の導電路(8)か形成されている。その導電路
(2)上にはトランジスタ、IC,LSIチップ等の複
数の回路素子(3)及びチップ抵抗、チップコンデンサ
ー等の複数の電子部品(3゛)が固着されている。A copper foil is adhered onto the substrate (1) via a thin insulating resin layer (not shown), and the copper foil is etched into a desired shape to form a conductive path (8) in a desired shape. A plurality of circuit elements (3) such as transistors, ICs, and LSI chips, and a plurality of electronic components (3) such as chip resistors and chip capacitors are fixed on the conductive path (2).
上記基板(1)上に固着された回路素子(3)及び電子
部品〈3゛)は基板(1)と固着される樹脂製のケース
材(4)とで密封封止されて形成された封止空間内で配
置される。The circuit element (3) and electronic component (3) fixed on the substrate (1) are hermetically sealed between the substrate (1) and the fixed resin case material (4). placed within the parking space.
ケース材(4〉は絶縁部材としての熱可塑性樹脂から形
成きれ、基板(1)と固着した際空間部が形成される様
に箱状に形成されている。その箱状のケース材(4)の
周端部は基板(1〉の略周端部に配置されて接着性を有
したシール剤(Jシート:商品名)によって基板(1)
と強固に固着一体止される。この結果、基板(1〉とケ
ース材(4)間に所定の封止空間部(8)が形成される
ことになる。更にケース材(4)には孔(5)が設けら
れている。その孔(5)は後述する半導体素子(7)の
挿脱を容易にするために半導体素子(7)より少し大き
めに形成諮れている。The case material (4) is made of thermoplastic resin as an insulating member, and is formed into a box shape so that a space is formed when it is fixed to the substrate (1).The box-shaped case material (4) The circumferential edge of the substrate (1) is sealed with an adhesive sealant (J-sheet: trade name) placed approximately at the circumferential edge of the substrate (1).
It is firmly fixed and fixed together. As a result, a predetermined sealed space (8) is formed between the substrate (1>) and the case material (4). Furthermore, a hole (5) is provided in the case material (4). The hole (5) is designed to be slightly larger than the semiconductor element (7) in order to facilitate the insertion and removal of a semiconductor element (7), which will be described later.
孔(5〉の周端辺には後述する蓋体(10)、!−螺着
させて半導体素子(7)を押圧接続させるのに寄与する
螺着部(5a)が設けられている。A lid body (10) to be described later is provided on the peripheral edge of the hole (5>), and a threaded part (5a) which contributes to the press connection of the semiconductor element (7) by threading is provided.
第2図は孔(5)が設けられたケース材(4)の要部拡
大平面図であり、矩形状の孔(5)が設けられたその周
端辺と点線との間の領域は螺着部(5a)であり、−点
鎖線で囲まれた領域は基板(1)と固着された領域を示
す。FIG. 2 is an enlarged plan view of the main part of the case material (4) in which the hole (5) is provided, and the area between the peripheral edge of the rectangular hole (5) and the dotted line is a screw hole. This is the attachment part (5a), and the area surrounded by the dashed line indicates the area fixed to the substrate (1).
螺着部(5a〉は孔(5〉の周端辺の一辺間でテーノく
面状に形成されている。即ち、第2図において、孔(5
)の各コーナ部をA、B、C,Dとすると、コーナAを
矢印Xの方向で見ると、孔(5)の螺着部(5a)は第
3図(X)の如く、Aでテーパ面が階段状に形成され、
また、コーナCを矢印Yの方向から見ると同図(Y)の
如く、Cでテーパ面が階段状に形成されている。即ち、
螺着部(5a)は孔(5)の各コーナ部において階段状
に形成きれている。The threaded part (5a) is formed in a rectangular shape between one side of the peripheral edge of the hole (5). In other words, in FIG.
) are A, B, C, and D. When corner A is viewed in the direction of arrow The tapered surface is shaped like a step,
Further, when corner C is viewed from the direction of arrow Y, as shown in the same figure (Y), the tapered surface at C is formed in a step-like shape. That is,
The threaded portions (5a) are formed stepwise at each corner of the hole (5).
ところで、孔(5)で露出した基板(1)上には板状の
導電性シート(6)が載置されている。導電性シート(
6)はゴム又は合成樹脂から成る弾性力を有する絶縁シ
ートで第4図に示す如く、板状に形成され、その厚さ方
向に線状導体(6a)が複数本埋め込まれており、導電
性シート(6)の両面からは複数の線状導体(6a)が
突出されている。斯る導電性シート(6)は特開昭62
−229714号公報、特開昭59−58709号公報
に記載されている。Incidentally, a plate-shaped conductive sheet (6) is placed on the substrate (1) exposed through the hole (5). Conductive sheet (
6) is an elastic insulating sheet made of rubber or synthetic resin, which is formed into a plate shape as shown in Fig. 4, and has a plurality of linear conductors (6a) embedded in its thickness direction, making it conductive. A plurality of linear conductors (6a) protrude from both sides of the sheet (6). Such conductive sheet (6)
It is described in Japanese Patent Application Laid-Open No. 59-58709.
この導電性シート(6)は孔(5)と同様もしくは若干
小さめに形成されており、このシート(5)上には樹脂
封止された半導体素子(7〉が載置される。This conductive sheet (6) is formed to be similar to or slightly smaller than the hole (5), and a resin-sealed semiconductor element (7) is placed on this sheet (5).
半導体素子(7)はEPROMSEEPROMマイコン
等の書き込み、消去可能なROMチップが樹脂封止され
た例えはフリッププロップ型の半導体素子(7)が用い
られる。その半導体素子(7)の底面には複数の電極(
7a)が設けられており、電極(7a)は導電性シート
(6)を介して導電路(2)と接続きれることになる。The semiconductor element (7) is, for example, a flip-flop type semiconductor element (7) in which a writable and erasable ROM chip such as an EPROM SEEPROM microcomputer is sealed with resin. The semiconductor element (7) has a plurality of electrodes (
7a) is provided, and the electrode (7a) can be connected to the conductive path (2) via the conductive sheet (6).
説明するまでもないか、孔(5)で露出した基板(1)
上には半導体素子(7)と接続するための複数の導電路
(2)が延在形成されている。Needless to explain, the substrate (1) exposed through the hole (5)
A plurality of conductive paths (2) for connecting to semiconductor elements (7) are formed extending on the top.
ケース材(5)で露出した基板(1)上に導電性シート
(6)、半導体素子(7)と順に搭載し蓋体(10)を
用いて半導体素子(7)を押圧接続する。即ち、孔(5
)のコーナ部に蓋体(10)の突出した端部(10a)
を挿入する様に配置し、螺着部(5a)のテーパ面のこ
う配が高い方に蓋体く10)を回転させる。すると、半
導体素子(7)は蓋体(10)の回転と伴に螺着押圧さ
れ、導電性シート(6)を介して導電路(2)と押圧接
続されることになる。本実施例では蓋体(10)の螺着
による押圧力を増加させるために半導体素子(7)の上
面に弾性力の富んだゴムシート(11)を配置している
。A conductive sheet (6) and a semiconductor element (7) are sequentially mounted on the substrate (1) exposed by the case material (5), and the semiconductor element (7) is pressed and connected using the lid (10). That is, the hole (5
) The protruding end (10a) of the lid (10)
is inserted, and the lid body 10) is rotated so that the slope of the tapered surface of the threaded portion (5a) is higher. Then, the semiconductor element (7) is screwed and pressed as the lid (10) rotates, and is pressed and connected to the conductive path (2) via the conductive sheet (6). In this embodiment, a highly elastic rubber sheet (11) is placed on the upper surface of the semiconductor element (7) in order to increase the pressing force due to screwing of the lid (10).
断る本発明に依れば、導電性シート(6)を用い且つ蓋
体(10)で半導体素子(7)を螺着押圧することで半
田付レスで、書き込み、消去可能な半導体素子(7)を
基板(1〉上の導電路(2)と接続することができる。According to the present invention, the semiconductor element (7) can be written and erased without soldering by using the conductive sheet (6) and screwing and pressing the semiconductor element (7) with the lid (10). can be connected to the conductive path (2) on the substrate (1>).
その結果、蓋体(10)をケース材(4)の孔(5)か
ら取りはずせば容易に半導体素子(7〉の交換か行える
。As a result, the semiconductor element (7) can be easily replaced by removing the lid (10) from the hole (5) of the case material (4).
(ト〉発明の効果
以上に詳述した如く、本発明に依れば、ケース材の所定
位置に孔を形成し、その孔で露出された基板上に導電性
シートを配置し、そのシート上に所定のプログラムデー
タを有する半導体素子を搭載してケース材の孔の周端辺
と蓋体とを螺着させ半導体素子を押圧接続することによ
り、半導体素子を半田付けすることなく導電路と接続す
ることができる。その結果、半導体素子の不良あるいは
データの書き変え等での交換が極めて容易に行える。(G) Effects of the Invention As detailed above, according to the present invention, a hole is formed in a predetermined position of the case material, a conductive sheet is placed on the substrate exposed by the hole, and a conductive sheet is placed on the substrate exposed through the hole. By mounting a semiconductor element having predetermined program data on the casing material, screwing the peripheral edge of the hole in the case material to the cover body, and connecting the semiconductor element with pressure, the semiconductor element can be connected to the conductive path without soldering. As a result, it is extremely easy to replace the semiconductor element due to a defect or data rewriting.
また、本発明では半導体素子は蓋体とケース材とで螺着
による押圧接続が行われるために、半導体零子と導電路
との接続強度の信頼性を向上することができる。Further, in the present invention, since the semiconductor element is press-connected by screwing between the lid and the case material, the reliability of the connection strength between the semiconductor wire and the conductive path can be improved.
更に、本発明の混成集積回路では半導体素子の検査と半
導体素子を組み込む前の混成集積回路との検査とが異な
るために多品種少量生産の場合、特に有効である。Further, in the hybrid integrated circuit of the present invention, the inspection of the semiconductor element and the inspection of the hybrid integrated circuit before incorporating the semiconductor element are different, so it is particularly effective in the case of high-mix low-volume production.
第1図は本発明の実施例を示す断面図、第2図はケース
材の要部拡大平面図、第3図はケース材の孔の螺着部を
示すための図、第4図は導電性シートを示す斜視図、第
5図、第6図および第7図は従来例を示す断面図である
。
(1)は集積回路基板、 (2)は導電路、 (3)は
回路素子、 (4〉はケース材、 (5)は孔、 (5
a)は螺着部、 (6)は導電性シート、 (7)は半
導体素子である。Fig. 1 is a sectional view showing an embodiment of the present invention, Fig. 2 is an enlarged plan view of the main part of the case material, Fig. 3 is a diagram showing the screwing part of the hole in the case material, and Fig. 4 is a conductive FIGS. 5, 6, and 7 are sectional views showing conventional examples. (1) is an integrated circuit board, (2) is a conductive path, (3) is a circuit element, (4> is a case material, (5) is a hole, (5)
a) is a screwed part, (6) is a conductive sheet, and (7) is a semiconductor element.
Claims (6)
の導電路と接続された複数の回路素子および樹脂封止型
半導体素子と 前記基板と一体化されるケース材とを具備し、前記ケー
ス材の所定位置に孔を設け、その孔で露出した前記基板
上に導電性シートを配置し、前記導電性シート上に前記
樹脂封止型半導体素子を搭載し、前記ケース材の孔の周
端辺と蓋体とを螺着させ前記半導体素子を押圧接続した
ことを特徴とする混成集積回路。(1) A case in which an integrated circuit board, a conductive path of a desired shape formed on the substrate, a plurality of circuit elements connected to the conductive path on the substrate, and a resin-sealed semiconductor element are integrated with the substrate. A hole is provided at a predetermined position of the case material, a conductive sheet is placed on the substrate exposed through the hole, and the resin-sealed semiconductor element is mounted on the conductive sheet, A hybrid integrated circuit characterized in that the semiconductor element is press-connected by screwing the peripheral edge of the hole of the case material to a lid body.
された封止空間に封止されることを特徴とする請求項1
記載の混成集積回路。(2) Claim 1, wherein the circuit element is sealed in a sealed space formed by the substrate and the case material.
Hybrid integrated circuit as described.
数の導電路が延在されたことを特徴とする請求項1記載
の混成集積回路。(3) The hybrid integrated circuit according to claim 1, wherein a plurality of conductive paths extend on the substrate on which the conductive sheet is disposed.
の両面から多数の線状導体が突出されることを特徴とす
る請求項1記載の混成集積回路。(4) The hybrid integrated circuit according to claim 1, wherein the conductive sheet is formed of an insulating sheet, and a large number of linear conductors protrude from both sides of the conductive sheet.
が設けられたことを特徴とする請求項1記載の混成集積
回路。(5) The hybrid integrated circuit according to claim 1, wherein a threaded portion for threading the lid is provided at a peripheral end of the hole.
徴とする請求項5記載の混成集積回路。(6) The hybrid integrated circuit according to claim 5, wherein the surface of the threaded portion is tapered.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2113121A JPH0410560A (en) | 1990-04-27 | 1990-04-27 | Hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2113121A JPH0410560A (en) | 1990-04-27 | 1990-04-27 | Hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0410560A true JPH0410560A (en) | 1992-01-14 |
Family
ID=14604057
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2113121A Pending JPH0410560A (en) | 1990-04-27 | 1990-04-27 | Hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0410560A (en) |
-
1990
- 1990-04-27 JP JP2113121A patent/JPH0410560A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TW452896B (en) | Semiconductor device, method of manufacture thereof, circuit board, and electronic device | |
| EP1906719A1 (en) | Electronic controller | |
| KR950004467A (en) | Semiconductor device and manufacturing method | |
| JPH03108744A (en) | Resin-sealed semiconductor device | |
| CN1763933B (en) | Printing circuit board and circuit unit introduced to same | |
| JP4020795B2 (en) | Semiconductor device | |
| JPH0410560A (en) | Hybrid integrated circuit | |
| US20080067660A1 (en) | Semiconductor device package | |
| JP2504486B2 (en) | Hybrid integrated circuit structure | |
| JPH047889A (en) | Hybrid integrated circuit | |
| JPH0717167Y2 (en) | Hybrid integrated circuit device | |
| JPH02135768A (en) | Hybrid integrated circuit | |
| JPH02135769A (en) | Hybrid integrated circuit | |
| JPH04350958A (en) | Heat dissipator of semiconductor integrated circuit | |
| JP3123917B2 (en) | Hybrid integrated circuit device | |
| JPH0760884B2 (en) | Hybrid integrated circuit device | |
| JPS59123291A (en) | Circuit board for electronic device | |
| KR20090049015A (en) | Circuit module | |
| JPH0739244Y2 (en) | Hybrid integrated circuit device | |
| JP2000124251A (en) | Semiconductor device and its manufacturing method, circuit board, and electronic equipment | |
| JP3409380B2 (en) | Printed circuit board device | |
| JP3615236B2 (en) | Hybrid integrated circuit device | |
| JPH0714938A (en) | Hybrid integrated circuit device | |
| JPH02163988A (en) | Hybrid integrated circuit | |
| JPH0430565A (en) | High power output hybrid integrated circuit device |