JPH0410567A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To improve a memory cell in reliability by a method wherein a slit is provided between the first and the second contact hole of tie closest memory cell extending from one end of a first grounding wire toward the other first contact hole. CONSTITUTION:The source N<+> diffusion layers of drive transistors Q1 and Q2 of a memory cell are separately connected to a polysilicon grounding wire 3, and the grounding wire 3 is provided in parallel with a word line 2 of a polycide layer and connected to an aluminum grounding wire 4 at every prescribed distance. A slit SL is provided to a polysilicon layer between a contact hole 35 which connects a source N<+> diffusion layer 32 of drive transistors Q1 of a memory cell located closest to the contact of a set line to the grounding wire 3 and a contact hole 35 used for connecting the layer 32 to the grounding wire 4, and the slit SL is made to reach to the vicinity of a contact 37 of a source N<+> diffusion layer 33 of drive transistors Q2 and formed as small in width as a patterning technique can permit. In result, a voltage drop can be prevented from occurring in a first grounding wire and a memory cell can be improved in reliability.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor device using a polysilicon layer as a ground wiring of a memory cell.

[Prior Art] Conventionally, as shown in FIGS. 4 and 5, this type of semiconductor memory device has a ground &I 43 made of a polysilicon layer disposed parallel to a word line 42 made of a polycide layer.
, a ground line 44 made of an aluminum layer arranged approximately every 8 or 16 bits perpendicular to the word line 42, and a drive transistor Ql.

Q2 and transfer transistor Q3. Q4 and a resistor 46 made of a high-resistance polysilicon layer.The source electrodes 51 and 52 of the two drive transistors Q1 and Q2 of the static memory cell are connected to different contact holes CI. , C2 are connected to a ground line 43 made of a polysilicon layer, and the ground line 43 is further connected to a ground line 44 made of an aluminum layer via a contact hole 45. The shape of the ground line 43 made of a polysilicon layer was made as wide as possible in order to lower wiring resistance, and was formed into a single wide plate, although there were some irregularities. Note that 53, 54 are source electrodes of other memory cells, and 58.degree. and 59 are contact holes thereof.

FIG. 6 shows the connection between the conventional static type memory cell having such a configuration and the ground lines 43 and 44. As shown in FIG. 6, a plurality of static type memory cells Ml, M
2. M3. M4 is connected to common ground lines 43 and 44, and is the source ground terminal A.

The potential of B is roughly estimated as follows.

When the transfer gate is in the on state, the current value flowing into the ground terminal per cell is assumed to be 10.

Consider only 4 bits. If RpO is the resistance value of the polysilicon layer, VA=VC=4i0・RpO VB=4 io・(RpO+Rpl) +2 io・R
Note that Rpl is a polysilicon resistor and Rnl is an N layer resistor. Therefore, the potential difference between point A and point B is VB-VA
=i0・(4Rpl+2 RNI)General ζIf the number of cell arrays is N, then VB-VA=jO・(NRpl
+2RN1), and as the number of cell arrays increases, A,
It is clear that the potential difference between 8 and 8 becomes large.

[Problem to be Solved by the Invention] In the conventional semiconductor memory device described above, when a current flows through the ground wiring of the memory cell, a potential difference occurs depending on the location of the wiring due to the layer resistance of the polysilicon forming the ground line 43. . In other words, the current flowing through the ground line polysilicon layer flows toward the contact 45 that is connected to the aluminum ground line 44, so the potential difference is
As a result, the potential gradient due to the polysilicon layer resistance also increases as the potential gradient approaches the contact 45. Under these circumstances, when focusing on the source electrodes 51 and 52 of the memory cell driving transistors Ql and Q2, the contacts C1 and C2 between the two source electrodes and the polysilicon ground line 43 are
In terms of layout, some are close to the aluminum grounding wire 44 and others are far away. However, originally the drive transistor Q
Although the source electrodes of I and Q2 should be at the same level, in reality, a potential difference occurs, and in the memory cell closest to the aluminum ground line 44,
This potential difference is at its maximum, which poses a problem in that malfunctions are likely to occur. That is, when the source potentials of the driving transistors Ql and Q2 of the same memory cell are different, the threshold voltages of the driving transistors Ql and Q2 appear to be different, and undesired inversion is likely to occur.

[Means for Solving the Problems] The gist of the present invention is to provide a memory cell in which a pair of series-connected drive transistors and a resistor are connected in parallel, and the gate of one drive transistor is connected to the drain of the other drive transistor. The resistors of the plurality of memory cells are each connected to a first grounding line through a first contact hole, and a second grounding line is connected at one end of the first connection line through a second contact hole. In a semiconductor memory device connected to a ground line, a connection is made between one of the first contact holes of the memory cell closest to the second contact hole and the second contact hole from one end of the first ground line to the second contact hole. A slit extending toward the other first contact hole of the memory cell is formed closest to the slit.

[Operation of the Invention] The slit formed in the first ground line described above is caused by current flowing into the first ground line from a plurality of memory cells except the memory cell closest to the second contact and flowing toward the second contact. A voltage drop of less than 100% is not caused to occur between the pair of first contacts of the memory cell closest to the second contact. Therefore, no apparent threshold difference occurs in the drive transistor of the memory cell closest to the second contact, and stable operation can be obtained.

[Example code] Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view showing the layout of a semiconductor memory device according to an embodiment of the present invention. A memory cell constituting a semiconductor memory device includes a flip-flop constituted by a pair of inverters consisting of a polysilicon high resistance element 6 and a drive transistor 7 (Ql, Q2), and a transfer gate TG. Transistor Ql
, Q2 are independent and connected to a polysilicon ground line 3 through different contact holes.The ground line 3 of the polysilicon layer is arranged parallel to the word line 2 of the polycide layer. The source N diffusion layer 32 of the drive transistor Q1 of the memory cell located closest to the contact of the ground line 4 is connected to the aluminum ground line 4 via contact holes 5 at predetermined distances. It is connected to the polysilicon wiring 3 for the ground line in the same way as the point, but this N゛ diffusion layer 32 and the polysilicon ground line 3
As shown in detail in FIG. 3, the polysilicon layer for the ground line 3 is provided with a slit SL between the contact hole 36 for connecting the aluminum ground line 4 and the contact hole 35 for connection with the aluminum ground line 4.
is provided. Slit SL is the source N of the other drive transistor Q2 + contact 37 of the diffusion N33
, and its width is the smallest possible value for patterning. In FIG. 3, reference numeral 34 indicates a source N+ diffusion layer of another memory cell, and reference numeral 38 indicates a contact hole thereof.

FIG. 2 is a schematic diagram of the ground wiring resistance network of the memory cell array of this embodiment. Potential difference V between the source potentials A and B of the memory cell Mll closest to the aluminum ground line 4
For example, in the cell data state shown in the figure, B-A is VB-A=2i0・RNI, but in conventional memory cell arrays, a potential gradient term is included due to the total current value proportional to the number of cells. On the other hand, in this embodiment, the potentials at points A and B are determined by the current flowing toward the common node C, and the potential difference generated between points A and 8 is smaller and has a value that does not depend on the number of memory cell arrays.

On the other hand, in memory cell M12, a potential difference still occurs between B and D due to the potential gradient caused by the current flowing through the polysilicon resistor Rp2, but by providing a slit in the ground polysilicon wiring, the difference between the ground aluminum wiring and the ground aluminum wiring is reduced. The value of the polysilicon resistance RpOO corresponding to the connection portion is twice or three times that of the conventional one. Since the polysilicon resistor RpO serves as a current limiter, the difference in source potential is smaller than that of the conventional memory cell M2.

In the above embodiment, the polysilicon ground line 3 constitutes the first ground line, the aluminum ground line 4 constitutes the second ground line, and the 3
5 functions as the second contact hole, and 36.37 functions as the first contact hole of the memory cell Mll closest to the second contact hole.

[Effects of the Invention] As explained above, the present invention provides a memory cell in which a pair of series-connected drive transistors and a resistor are connected in parallel, and the gate of one drive transistor is connected to the drain of the other drive transistor. The resistors of the plurality of memory cells are each connected to a first grounding line through a first contact hole, and a second grounding line is connected at one end of the first connection line through a second contact hole. In a semiconductor memory device connected to a ground line, a connection is made between one of the first contact holes of the memory cell closest to the second contact hole and the second contact hole from one end of the first ground line to the second contact hole. the other first of the memory cells closest to
By forming the slit extending toward the contact hole, the current flowing from the source terminal of another memory cell to the ground is directed to the two source terminals of the memory cell located closest to the second contact hole. There is no flow between the first ground wires. Therefore, no voltage drop occurs on the first ground line between them, and no apparent threshold difference occurs between the drive transistors of the pair of memory cells. Therefore, the operation of the drive transistor is stabilized, and the reliability of the memory cell is improved. In addition, for memory cells from the second contact hole onwards, the width is narrowed by making a slit in the first ground line, and the resistance is higher than before, so the first ground line This also has the effect of reducing the value of the current flowing into the second ground line from each connected memory cell, thereby reducing the potential difference between the two left and right source terminals of the memory cell.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing an embodiment of the present invention, FIG. 2 is a schematic diagram of a ground wiring network of a memory cell array according to an embodiment of the invention, and FIG. 3 is a plan view of an embodiment of the invention shown in FIG. FIG. 4 is a plan view of a conventional example; FIG. 5 is a plan view of a conventional example corresponding to FIG. 3;
FIG. 6 is a schematic diagram of a ground wiring network of a conventional memory cell array. 1.41...N1 diffusion layer, 2.42.
・・・・・・・・・Word line, 3, 43. 4. 4
4...Grounding wire, 35.45...Contact, 6.46...Resistor, 7.
47・・・・・・・・・Drive transistor, 8, 3
6. 37. 38. 48°58.59. CI, C2
...Ground contact, 9.49φ order...φ polysilicon contact, 10.50....Direct contact.

Claims (1)

[Claims] It has a plurality of memory cells in which a pair of series-connected drive transistors and a resistor are connected in parallel, and the gate of one drive transistor is connected to the drain of the other drive transistor, and the resistor of the plurality of memory cells is provided. are respectively connected to the first grounding wire through the first contact holes,
In a semiconductor memory device in which one end of the first connection line is connected to a second ground line through a second contact hole, one of the first contact holes and the second contact hole of a memory cell closest to the second contact hole; and a slit extending from one end of the first ground line to the second contact hole closest to the second contact hole and extending toward the other first contact hole of the memory cell.