JPH04106752A - Brake controller - Google Patents

Abstract

PURPOSE:To easily realize brake control at a microcomputer by detecting the inversion of a direction by operating a counter means. CONSTITUTION:When a first FG signal is inputted to a microcomputer 1, the state of a direction error discrimination proofing flag is checked and when the state is an H level, a speed control processing is executed. When the state is an L level, '1' is added to the count value of a first counter 15 and it is investigated whether the count value of the first counter 15 is equal to '2' or not. When the value is not equal to '2', '1' is subtracted from the count value of a second FG counter 16. When the value is equal to '2', the generation of inversion is judged, a forward/backward instructing signal H is set at the L level (to instruct the forward direction), and a T2 timer is set. Namely, forward rotation is instructed to a capstan motor 2 and the motor is driven forward during the period of T2. Thus, the inverted component of a tape is compensated.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a brake control device for a recording/reproducing apparatus using a tape-shaped recording medium such as a video tape recorder.

(b) Conventional technology In a recording/reproducing apparatus such as a video tape recorder, the tape is driven intermittently.

This realizes slow motion playback by driving the tape intermittently. By the way, in this case, the tape starts running in synchronization with rotation and de.
Generally, application of the brake is executed at a predetermined timing after the regeneration control signal is obtained. In systems where playback control signals are not utilized, other positioning means are utilized.

What ultimately determines where the tape stops is the application of the brake to the capstan motor. Normally, the brake is applied by supplying a brake pulse to the capstan motor, but if the brake is not the right size, the playback quality will be affected.

Therefore, conventionally, a two-phase FG multiplication signal is obtained from the capstan motor, and the reversal of the capstan motor is checked from the mutual phase relationship of the two-phase FG signals, and brake pulse application is stopped. We are trying to optimize the grant (Utility Model Application No. 62-67331, G11B15/46
7).

(Hano Problems to be Solved by the Invention By the way, the above-mentioned prior art is constituted by hardware, and cannot be implemented as is if realized by a microcomputer.

(d) Means for Solving the Problems Therefore, in the present invention, as a configuration that can be realized by a microcomputer, the edges of the first FG multiplier signal are increased in relation to the rising and falling edges, and the rising and falling edges of the second FG multiplier signal are increased. a first counter means that is decremented in relation to a falling edge of the first FG multiplier signal; a first counter means that is decremented in relation to a rising/falling edge of the first FG multiplier signal; and a means for detecting that the count values of the first and second counter means are at predetermined values, and controlling the brake pulse based on the output of the predetermined value detection means. That's what I do.

(e) Effect: In other words, when the phase relationship between the first FG multiple signal and the second FG multiple signal is constant, the values of these counters will not reach the predetermined value, but the rotation of the capstan will be reversed. If this happens, the phase relationship will collapse and the contents of the counter will change. Therefore, a reversal of the tape running direction can be detected.

(f) Examples Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the embodiment, FIGS. 2, 3, 4, and 5 are flow charts showing operations, and FIG. 6 is a waveform diagram.

In the figure, 1 is a microcomputer that performs brake control and other operations, 2 is a capstan motor, 3 is a motor drive circuit, 4 is a playback control head, and 5 is an RF
SW pulse input terminal, 6 is speed control means, 7 is trunking delay means, 8 is RF delay means, 9 is forward/reverse direction specifying means, IQ:: first FG detection means, 11 is second checking means, 12 13 is a direction determining means, 13 is a first edge detecting means, 1
4 is a second edge detection means, 15 is a first counter, 16 is a second counter, 17 is a first detection means, 18 is a second detection means, and 19 is a brake correction means.

Each element is composed of a microcomputer 1.

In intermittent drive slow playback, tape running is started in accordance with the timing of RFSW (a signal synchronized with the rotating head and used for switching signals from the head), and tape running is started. Then, a brake pulse is applied to the capstan motor at a timing delayed by a predetermined time from the timing of the reproduced control signal to brake the tape.

The detailed state of this operation is shown in FIG. In Fig. 5, A indicates the RF SW, B indicates the playback control signal,
C is the CTL interrupt, D is the tracking timer, E is the pre-correction brake pulse, F is the first FG signal, and G is the second
FG signal, H indicates forward/reverse instruction signal, ■ indicates capstan correction signal, and J indicates brake pulse.

Next, the operation will be explained. When the tape is driven and a playback control signal is generated, the microcomputer 1
A TL interrupt occurs and the TI timer is incremented. This digit 1 is a delay time for tracking. When this timer expires, the timer interrupt 20 shown in FIG. 2 is executed. T] For the timer interrupt, set the forward/reverse instruction signal to I level (instructing the reverse direction), set the brake pulse to H level, reset the direction misjudgment prevention flag, and cancel the interrupt of the first FG signal. Changed to Jigara Artwork, Ji detection, and the second
Switch to both edge detection while FG signal interrupt is disabled,
Reset the first and second counters.

Then, each time the first and second FG signals are generated, an FG interrupt 21 occurs in the microcomputer 1, and as shown in FIG.
The processing shown in FIG. 4 is performed.

That is, when the first FG signal is input, the state of the direction error determination prevention flag is checked and if it is at the LH level, speed control processing is performed. If it is at L level, the count value of the first counter 15 is increased by one, and it is checked whether the count value of the first counter 15 is equal to 2. If not, the count value of the second FG counter 16 is decreased by one. If it is equal to 2, it is determined that an inversion has occurred, the forward/reverse instruction signal H is set to L level (instructing the forward direction), and the T2 timer is set.

Further, the direction misjudgment prevention flag is set to H level.

Then return to the beginning (1st FG interrupt processing 21A) - 2nd F
In the G interrupt processing 21B, almost the same operation is performed.

When the 12 hours expire, a T2 timer interrupt 22 is executed. In this process, in order to stop the capstan motor 2, the level of the motor drive terminal (not shown) is set to L level. Then, the interruption of the first FG signal is limited to only one edge, the interruption of the second FG signal is prohibited, and the process returns.

In other words, in terms of brake operation, at the stage when a reversal is detected, the capstan motor 2 is instructed to rotate in the forward direction, and T2
is driven in the positive direction for a period of . This compensates for tape inversion.

The reason why the rotation direction can be determined is because the operation is as follows. As long as the motor is rotating in the forward direction, the phase relationship between the two FG multiplier signals will not change, and the count values of the first and second counters will increase and decrease, until the count value becomes 2. It won't happen. However, when the direction of rotation is reversed, the count value becomes 2 because it is increased before being decreased.

In the above explanation, the counters have been described as first and second counters, but they are actually just registers whose values are incremented and decremented.

In the above embodiment, the direction misjudgment prevention flag was set to the L level at the time of the T1 interrupt, but this flag was set to the L level at the time of the T1 interrupt.
It can also be done during interrupt processing. That is, as shown in FIG. 7, during the speed control process, it is checked whether the measured FG multiplied signal period A is larger than a predetermined value a, and when it is larger, the misjudgment prevention flag is set to L level. In this way, processing for each direction can be stopped until the FG cycle becomes larger than a predetermined value. This method is effective when the speed control process cannot be executed unless the frequency of the FG multiplied signal is divided and the interrupt process is performed. In other words, speed control is frequency division.
Although a G-multiple signal is also possible, direction determination cannot be performed without using the direct FG from the capstan motor. This is necessary when the tape speed is fast as in the standard mode and the microcomputer processing speed is slow.

(Effects of the Invention) As described above, according to the present invention, since the reversal of direction is detected by the operation of the counter means, it can be easily realized even in a microcomputer.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the configuration of the embodiment, Figures 2 and 3.
4 and 5 are flowcharts showing the operation, and FIG. 6 is an explanatory diagram τ of the operation. FIG. 7 is a flowchart of another embodiment. I... Microcomputer, 2... Capstan motor, 15... First counter, 16... First counter, 20... TI timer interrupt, 21... FG interrupt, 21, A... 1st FG interrupt processing, 21B... 2nd FG interrupt processing, 22... T2 timer interrupt.

Claims (1)

[Claims] (1) a first counter means that increases in relation to the rising and falling edges of the first FG signal and decreases in relation to the rising and falling edges of the second FG signal;
a second counter means which decreases in relation to the rising and falling edges of the second FG signal and increases in relation to the rising and falling edges of the second FG signal, and these first and second counters; 1. A brake control device comprising: means for detecting that a count value of the means is a predetermined value; and a brake pulse is controlled based on the output of the predetermined value detecting means.