JPH04106928A - Formation of oxide film on the surface of compound semiconductor - Google Patents

Formation of oxide film on the surface of compound semiconductor

Info

Publication number
JPH04106928A
JPH04106928A JP22397090A JP22397090A JPH04106928A JP H04106928 A JPH04106928 A JP H04106928A JP 22397090 A JP22397090 A JP 22397090A JP 22397090 A JP22397090 A JP 22397090A JP H04106928 A JPH04106928 A JP H04106928A
Authority
JP
Japan
Prior art keywords
oxide film
compound semiconductor
ampoule
pbn
ampule
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22397090A
Other languages
Japanese (ja)
Inventor
Haruto Shimakura
島倉 春人
Osamu Oda
修 小田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Eneos Corp
Original Assignee
Nippon Mining Co Ltd
Nikko Kyodo Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Mining Co Ltd, Nikko Kyodo Co Ltd filed Critical Nippon Mining Co Ltd
Priority to JP22397090A priority Critical patent/JPH04106928A/en
Publication of JPH04106928A publication Critical patent/JPH04106928A/en
Pending legal-status Critical Current

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  • Formation Of Insulating Films (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE:To obtain a stabilized oxide film with a small interface level density by vacuum-sealing a compound semiconductor and an element with a higher vapor pressure and oxygen out of the components in a quartz ampule, and then thermally oxidizing. CONSTITUTION:A wafer cut out from InP single crystal is placed into a pBN- made vessel 1. This vessel is inserted into a quartz ampule 2 with the pBN-made vessel on which red phosphorus is mounted. After the ampule 2 is evacuated, oxygen gas is introduced. Then, the ampule 2 is sealed and heated in a heating furnace 10 where an oxide film is formed on the wafer 5. Under this construction, phosphorous is supplied to the front surface of the crystal from phosphorus vapor so as to prevent the shortage of phosphorous on the surface of the oxide film where uniform oxide film grows and moreover, the original surface of the substrate is covered with the oxide film. This construction makes it possible to obtain an oxide film having a small interface level density, minimize the mixture of impurities into the oxide film to be generated and hence enhance device characteristics.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は化合物半導体単結晶を基体とする電界効果型ト
ランジスタC以下FETと記す)の絶縁膜形成技術に関
し、特にInP単結晶およびその三元、四元混晶の基板
上にMOSFETやショットキ・ダイオードおよびME
SFETを形成する場合に利用して最も効果のある技術
に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a technology for forming an insulating film of a field effect transistor (hereinafter referred to as FET) based on a compound semiconductor single crystal, and in particular to an InP single crystal and its ternary , MOSFETs, Schottky diodes, and MEs on quaternary mixed crystal substrates.
This article relates to the most effective techniques to use when forming SFETs.

[従来の技術] GaAs、InPなどの化合物半導体は電子の移動度が
シリコンよりも高く、また耐放射線性、耐熱性などに優
れ、シリコンに代わる高周波、高速の電子デバイスとし
てその将来性が見込まれ、数多くの研究がなされてきた
が、界面準位密度の小さな安定な酸化膜が得られないた
め、G a A、 s単結晶やInP単結晶を基板とす
るMOSFETはまだ実用化されるに至っていない。そ
こで、GaAs単結晶を用いたデバイスとしては、ショ
ットキー電極を利用したMESFETが実用化され、デ
ィスクリートの高周波FETや、小規模のディジタルI
Cが実用化されている。しかし、GaAs M E S
 F E Tはショットキー障壁電位が小さいために、
ICを構成したとき論理振幅が大きくとれず、大規模の
ディジタルICを高歩留りで製造することができないと
いう欠点を有している。
[Prior Art] Compound semiconductors such as GaAs and InP have higher electron mobility than silicon, and also have excellent radiation resistance and heat resistance, and are expected to have future potential as high-frequency, high-speed electronic devices that can replace silicon. Although many studies have been conducted, MOSFETs using GaA,S single crystals or InP single crystals as substrates have not yet been put into practical use because stable oxide films with low interface state density have not been obtained. not present. Therefore, MESFETs using Schottky electrodes have been put into practical use as devices using GaAs single crystals, and have been used as discrete high-frequency FETs and small-scale digital I/O devices.
C has been put into practical use. However, GaAs MES
Since FET has a small Schottky barrier potential,
It has the disadvantage that when an IC is constructed, a large logic amplitude cannot be obtained, and a large-scale digital IC cannot be manufactured at a high yield.

一方、InP単結晶を基板とするデバイスとしては、Q
aAsに比べてショットキ障壁電位の小さいMESFE
TLかできないと考えられていた。
On the other hand, as a device using InP single crystal as a substrate, Q
MESFE with smaller Schottky barrier potential than aAs
It was thought that only TL could do it.

そのため、熱酸化法、陽極酸化法、プラズマ酸化法など
によりInP基板上に形成された酸化膜の上に金属層(
電極)を形成してなるMOSFETを作る努力がされて
きたが、いずれも酸化膜の組成が不均一となり、絶縁性
が悪く、良好なMOSFETが実現できず実用化される
には至っていない。このようなMOSFETに代わる方
法として、S i O,、S i Nx、AQ、03.
PNのような絶縁膜をInP基板上にCVD法、プラズ
マCVD法、光励起CVD法、スパッタ法、蒸着法、ス
ピンオン法などにより低温堆積させた上に金属層を形成
するMISFETの研究が数多くなされてきた。
Therefore, a metal layer (
Efforts have been made to create MOSFETs by forming electrodes), but in all cases, the composition of the oxide film is non-uniform, the insulation is poor, and good MOSFETs cannot be realized, so they have not been put into practical use. As an alternative to such MOSFETs, S i O,, S i Nx, AQ, 03.
Many studies have been conducted on MISFETs in which a metal layer is formed on an insulating film such as PN deposited on an InP substrate at a low temperature by CVD, plasma CVD, photo-enhanced CVD, sputtering, vapor deposition, spin-on, etc. Ta.

[発明が解決しようとする課題] しかしながら、上記方法により製造されたMISFET
はいずれもドレイン電流がドリフトするという電子デバ
イスとしては致命的な欠点を有しており、実用化される
には至っていない。
[Problem to be solved by the invention] However, the MISFET manufactured by the above method
All of these have a fatal drawback as an electronic device in that the drain current drifts, and so they have not been put into practical use.

ところでさきに述べたように、化合物半導体においては
MOSFETが実用化されていないが、その原因は酸化
膜の組成が不均一となることである。
By the way, as mentioned earlier, MOSFETs have not been put to practical use in compound semiconductors, and the reason for this is that the composition of the oxide film becomes non-uniform.

例えばInPの場合、酸素中で熱酸化させると当初はI
nP○、が20人はど成長するが、その後は、Inより
もPの拡散速度が遅いためにInPO4膜の外側にIn
、03膜が、またInPと1nP○4の界面にはPが析
出することが知られている。このような現象は陽極酸化
や、プラズマ酸化などのいずれの方法であっても起こり
、均一で良質な酸化膜が得られない原因となっている。
For example, in the case of InP, when it is thermally oxidized in oxygen, initially I
nP○ grows for about 20 minutes, but after that, because the diffusion rate of P is slower than that of In, In
, 03 film, and P is known to precipitate at the interface between InP and 1nP◯4. This phenomenon occurs regardless of the method used, such as anodic oxidation or plasma oxidation, and is the reason why a uniform and high-quality oxide film cannot be obtained.

また、P、01゜ガス中で酸化膜を形成する場合、蒸気
圧供給源としてP、O,(固体)を用いると、p、o、
<固体)は結晶構造により蒸気圧が変わる上に空気中の
水分を吸収しやすく、封管中に水分を持ち込むため、蒸
気圧の制御が難しく、良質の酸化膜を安定して得るのは
難しい。
In addition, when forming an oxide film in P,01° gas, if P, O, (solid) is used as the vapor pressure source, p, o,
(Solid) has a vapor pressure that changes depending on its crystal structure, and also easily absorbs moisture from the air, bringing moisture into the sealed tube, making it difficult to control the vapor pressure and making it difficult to consistently obtain a high-quality oxide film. .

このように、熱酸化によっては良質な絶縁膜ができにく
いために、先に述べたような種々の低温堆積法が研究さ
れているわけであるが、堆積法では化合物半導体基板の
表面上に別の系の物質を堆積させるために、絶縁膜と化
合物半導体基板の界面で格子不整合が起こる他、表面の
欠陥、汚れなどにより、界面には多くの界面準位が形成
されやすく、これによってドレイン電流がドリフトを起
こすという問題点がある。
As described above, it is difficult to form a high-quality insulating film by thermal oxidation, so various low-temperature deposition methods as mentioned above are being researched. In addition to the lattice mismatch that occurs at the interface between the insulating film and the compound semiconductor substrate due to the deposition of a system of There is a problem that current drift occurs.

この発明の目的は、InP系の化合物半導体基板を用い
て界面準位密度が小さく安定かつ含有不純物の少ない酸
化膜を形成する技術を提供することにある。
An object of the present invention is to provide a technique for forming an oxide film having a low interface state density, stable, and containing few impurities using an InP-based compound semiconductor substrate.

[問題点を解決するための手段] S1単結晶を基板とするMOSFETにおいては、シリ
コンの酸化膜を形成する際、S i / S iO,界
面はもともとのシリコン基板の表面ではなく、酸化に伴
って酸素が酸化膜中を拡散して基板のSiと反応するた
め、界面はもとの結晶の内部に形成されるようになる。
[Means for solving the problem] In a MOSFET using an S1 single crystal as a substrate, when forming a silicon oxide film, the Si/SiO interface is not the original surface of the silicon substrate, but a Since oxygen diffuses through the oxide film and reacts with Si in the substrate, an interface is formed inside the original crystal.

このため、Si基板では基板表面の欠陥などに影響され
ない低界面準位密度が実現でき、それゆえにMOSFE
Tが実用化されている。
For this reason, Si substrates can achieve a low interface state density that is unaffected by defects on the substrate surface, and therefore MOSFE
T has been put into practical use.

以上の点を総合的に検討すると、化合物半導体のFET
を実現するためには、熱酸化膜を絶縁膜とするのが最も
良い方法と考えられる。
Comprehensively considering the above points, compound semiconductor FET
In order to achieve this, it is considered that the best method is to use a thermal oxide film as an insulating film.

ところで、熱酸化膜を用いたInPのMOSデバイスに
関しては、酸素中での熱酸化の他、高圧酸素中での熱酸
化、p、 o、蒸気中での熱酸化、HNO3溶液中での
酸化、p、o、を蒸着させた後、これを加熱して酸化さ
せる方法など、従来いくつかの方法が検討されてきたが
いずれも不十分なものであり、MOSFETは実用化さ
れるに至っていない。その原因としては、結晶表面の酸
化膜の組成が不均一となり、一部で絶縁性の悪い酸化物
が形成されていることにあるとの結論に達した。
By the way, regarding InP MOS devices using thermal oxide films, in addition to thermal oxidation in oxygen, thermal oxidation in high pressure oxygen, thermal oxidation in p, o, steam, oxidation in HNO3 solution, Several methods have been studied in the past, such as depositing p, o, and then heating and oxidizing them, but all of them are insufficient, and MOSFETs have not yet been put into practical use. It was concluded that the cause of this was that the composition of the oxide film on the crystal surface became non-uniform, and oxides with poor insulation properties were formed in some areas.

そこで本発明は、化合物半導体基板上に酸化膜を形成す
るにあたり、半密閉型のpBN製容器に入れた上記化合
物半導体基板を化合物半導体基板の構成元素のうち蒸気
圧の高い元素とともに石英製アンプル中に挿入して、該
アンプル内を真空にしてから酸素ガスを導入した後アン
プルを封止し、このアンプルを加熱するようにしたもの
である。
Therefore, in forming an oxide film on a compound semiconductor substrate, the present invention provides that the compound semiconductor substrate placed in a semi-closed pBN container is placed in a quartz ampoule together with an element having a high vapor pressure among the constituent elements of the compound semiconductor substrate. The ampoule is inserted into the ampoule, the inside of the ampoule is evacuated, oxygen gas is introduced, the ampoule is sealed, and the ampoule is heated.

Pと○、の量は(1)式の反応で残ったリン(P、)圧
がストイキオメトリ−のInPの酸化膜形成温度での平
衡リン圧近くとなるように制御する。
The amounts of P and O are controlled so that the phosphorus (P,) pressure remaining from the reaction of equation (1) is close to the equilibrium phosphorus pressure at the stoichiometry InP oxide film formation temperature.

P+0.→P706+P4・・・・(1)[作用コ 本発明によれば、例えば基板がInPの場合には、アン
プル中に予めP(リン)及び02(酸素)を入れるため
、リン蒸気から結晶表面側へリンが補給されて酸化膜表
面がリンネ足になるのが防止され、均一な酸化膜が成長
し、かつ酸化膜成長に伴ってもとの基板表面が酸化膜中
に取り込まれ、界面準位密度の小さな酸化膜が得られる
とともに、基板をpBN製容器に入れてアンプル中に封
入しているため、そのままアンプルに入れて封入する場
合に比べて生成される酸化膜中への石英アンプルからの
不純物の混入が棲めて少なくなり、この酸化膜を用いた
デバイスの特性を向上させることができる。
P+0. →P706+P4...(1) [Operation According to the present invention, for example, when the substrate is InP, P (phosphorus) and 02 (oxygen) are placed in the ampoule in advance, so that the crystal surface side is removed from the phosphorus vapor. Herrin is replenished and the oxide film surface is prevented from forming Linnean legs, a uniform oxide film grows, and as the oxide film grows, the original substrate surface is incorporated into the oxide film, increasing the interface level. In addition to obtaining a low-density oxide film, since the substrate is placed in a pBN container and sealed in the ampoule, it is less likely that the oxide film that is formed will be absorbed by the quartz ampule compared to the case where the substrate is placed in the ampoule and sealed. The contamination of impurities is significantly reduced, and the characteristics of devices using this oxide film can be improved.

[実施例コ 直径2インチのアンドープn型のInP単結晶をLEC
法で育成し、引上げ軸と直交する方向に切断し、切り出
されたウェーハを鏡面研摩加工し有機溶剤で洗浄後、ブ
ロームメタノールでエツチングし、その後、酸化直前に
HF(フッ酸)で洗浄した。使用したウェーハのキャリ
ア濃度は、(4〜6) X 10”am−″である。
[Example] An undoped n-type InP single crystal with a diameter of 2 inches was subjected to LEC.
The wafers were grown by the method, cut in a direction perpendicular to the pulling axis, and the cut wafers were mirror-polished, washed with an organic solvent, etched with brome methanol, and then washed with HF (hydrofluoric acid) immediately before oxidation. The carrier concentration of the wafer used was (4-6) x 10"am-".

このウェーハを、第1図に示すようにpBN製の容器1
に入れてから、この容器1を赤リンをのせたpBN製の
器3とともに石英アンプル2内に挿入した。この石英ア
ンプル2内を真空にした後、酸素ガスを0.1〜0.3
atm(室温)導入してからアンプルを封止し、加熱炉
IO内に設置した。
This wafer is placed in a pBN container 1 as shown in FIG.
Then, this container 1 was inserted into a quartz ampoule 2 together with a pBN vessel 3 on which red phosphorus was placed. After making the inside of this quartz ampoule 2 a vacuum, add 0.1 to 0.3 of oxygen gas.
After introducing ATM (room temperature), the ampoule was sealed and placed in a heating furnace IO.

この石英アンプル2を、加熱炉10内にで450℃〜7
00℃で5〜20時間加熱し、ウェーハ5上に酸化膜を
形成した。
This quartz ampoule 2 is heated to 450°C to 7°C in a heating furnace 10.
The wafer 5 was heated at 00° C. for 5 to 20 hours to form an oxide film on the wafer 5.

第2図(a)、(b)にpBN製の容器1の構成例を示
す。容器1は片側に底を有する筒状容器la、lbから
なり、2個の筒状容器を互いに嵌め合わすことで密閉に
近い状態になるように構成されている。また、下部には
真空引きするため直径0.5mmの小さな穴1cが開け
てあり、容器1の外径はアンプル2の内径より若干小さ
い程度とした。InPウェーハ5はpBN製の支持台4
に載せて容器1内に入れてアンプル2内に間接的に設置
した。アンプル内のリンの量としては、加熱時の圧力が
0.2〜2.Oatmとなる量を決定し、封入した。な
お、上記pBN製容器lおよび支持台4は空気中で90
0℃で2時間ベーキングしてから使用した。
FIGS. 2(a) and 2(b) show an example of the structure of the container 1 made of pBN. The container 1 consists of cylindrical containers la and lb each having a bottom on one side, and is constructed so that the two cylindrical containers are fitted together to create a nearly hermetically sealed state. Further, a small hole 1c with a diameter of 0.5 mm was opened in the lower part for evacuation, and the outer diameter of the container 1 was slightly smaller than the inner diameter of the ampoule 2. The InP wafer 5 is mounted on a support stand 4 made of pBN.
It was placed on the container 1 and placed indirectly in the ampoule 2. As for the amount of phosphorus in the ampoule, the pressure during heating is 0.2 to 2. The amount to be Oatm was determined and sealed. Note that the pBN container 1 and the support stand 4 were heated for 90 minutes in air.
It was used after baking at 0°C for 2 hours.

上記方法により酸化膜が形成されたウェーハの酸化膜を
評価するためウェーハの一方の面にレジストを塗付し、
オーミック電極を形成させるため他方の面の酸化膜をラ
ッピングとブロム系のエッチャントで除去した後、Au
−Geからなる積層構造の金属層を蒸着した。次に、上
記レジストを除去した後、N、ガス中で350’Cで5
分間アニールして酸化膜除去面にAu−Ge積層構造の
オーミック電極を形成した。さらに、ウェーハの酸化膜
が残っている側の面に、金属をマスクに用いて直径0.
3mm、間隔1mmでAQ電極層を蒸着し、MOSキャ
パシタを作成した。
In order to evaluate the oxide film of the wafer on which the oxide film was formed by the above method, a resist was applied to one side of the wafer.
After removing the oxide film on the other side by lapping and using a bromine-based etchant to form an ohmic electrode, the Au
A layered metal layer consisting of -Ge was deposited. Next, after removing the above resist, it was heated at 350'C in N gas for 50 minutes.
An ohmic electrode having an Au-Ge laminated structure was formed on the surface from which the oxide film had been removed by annealing for a minute. Furthermore, a metal mask was used as a mask to coat the surface of the wafer on which the oxide film remained with a diameter of 0.
AQ electrode layers were deposited with a thickness of 3 mm and an interval of 1 mm to create a MOS capacitor.

第3図に、作成したMOSキャパシタについて測定した
C−V特性を示す。
FIG. 3 shows the CV characteristics measured for the produced MOS capacitor.

従来法によると、C−■特性の電圧軸方向のシフト量が
2v以上あったものが本実施例では第3図から明らかな
ように、ヒステリシスの電圧軸方向のシフト量が0.2
5V以下である優れた絶縁膜が形成できた。このことは
、本発明で示している方法が、InP単結晶を基板とす
るMOSFETのドレイン電流ドリフト現象の低減に極
めて有力なことを示している。また、ターマン法で測定
した界面準位密度はl X 10”cm−’ e V−
1以下であり、本発明により、界面準位密度の小さい良
質の絶縁膜が形成されていた。なお、形成された酸化膜
の厚さは約45OAであった。
According to the conventional method, the shift amount of the C-■ characteristic in the voltage axis direction was 2V or more, but in this embodiment, as is clear from FIG. 3, the shift amount of the hysteresis in the voltage axis direction is 0.2V.
An excellent insulating film with a voltage of 5V or less was formed. This shows that the method shown in the present invention is extremely effective in reducing the drain current drift phenomenon of MOSFETs using an InP single crystal as a substrate. In addition, the interface state density measured by the Terman method is l x 10"cm-' e V-
1 or less, and a high-quality insulating film with a low interface state density was formed by the present invention. Note that the thickness of the formed oxide film was about 45 OA.

第4図にSIMS分析による酸化膜の表面から約110
0nの深さまでの不純物(Si、Zn)量の分布を表す
。同図(a)はpBN製容器1を使用して酸化膜を形成
した場合、同図(b)はpBN製容器1を使用しないほ
かは同一条件で酸化膜を形成した場合である。なお、縦
軸にはInとのスペクトル強度の比で不純物量を示しで
ある。同図より、上記実施例を適用することによって酸
化膜中の81とZnが著しく減少することが分かる。
Figure 4 shows approximately 110 mm from the surface of the oxide film according to SIMS analysis.
It represents the distribution of the amount of impurities (Si, Zn) up to a depth of 0n. FIG. 5(a) shows the case where the oxide film was formed using the pBN container 1, and FIG. 2(b) shows the case where the oxide film was formed under the same conditions except that the pBN container 1 was not used. Note that the vertical axis shows the amount of impurities as a ratio of spectral intensity to In. From the figure, it can be seen that by applying the above embodiment, 81 and Zn in the oxide film are significantly reduced.

このことからpBN製容器1を使用しない場合に酸化膜
中に含まれるSlは、石英アンプルからの混入と考えら
れる。
From this, it is considered that Sl contained in the oxide film when the pBN container 1 is not used is mixed in from the quartz ampoule.

上記実施例では2個の筒状容器を嵌合させて半密閉型容
器1を構成しているが、円筒容器とその上部を覆う蓋と
によシバ半密閉容器を構成するようにしてもよい。
In the above embodiment, two cylindrical containers are fitted together to constitute the semi-closed container 1, but a cylindrical container and a lid covering the top may constitute a semi-closed container. .

[発明の効果〕 以上説明したようにこの発明は、石英アンプル中に化合
物半導体の構成元素のうち蒸気圧の高い方の元素および
その酸素を上記化合物半導体基板とともに真空封入した
後、熱酸化させるにあたり、上記化合物半導体の構成元
素のうち蒸気圧の高い元素をアンプル中に入れるととも
に、化合物半導体基板をpBN製の容器内に入れて直接
石英アンプルの内壁に臨まないようにしてアンプル中に
封入るようにしたので、例えば基板がInPの場合には
、アンプル中に予めP(リン)及び02(酸素)を入れ
るため、リン蒸気から結晶表面側へリンが補給されて酸
化膜表面がリンネ足になるのが防止され、均一な酸化膜
が成長し、かつ酸化膜成長に伴ってもとの基板表面が酸
化膜中に取iノ込まれ、界面準位密度の小さな酸化膜が
得られるとともに、基板をpBN製容器に入れてアンプ
ル中に封入しているため、そのままアンプルに入れて場
合に比べて生成される酸化膜中への不純物の混入が極め
て少なくなり、この酸化膜を用いたデバイスの特性を向
上させることができるという効果がある。
[Effects of the Invention] As explained above, the present invention provides a method for thermally oxidizing an element having a higher vapor pressure among the constituent elements of a compound semiconductor and its oxygen after vacuum-sealing it together with the compound semiconductor substrate in a quartz ampoule. Among the constituent elements of the compound semiconductor, an element with a high vapor pressure is placed in an ampoule, and the compound semiconductor substrate is placed in a pBN container and sealed in the ampoule so as not to directly face the inner wall of the quartz ampoule. For example, if the substrate is InP, P (phosphorus) and 02 (oxygen) are added to the ampoule in advance, so phosphorus is supplied from the phosphorus vapor to the crystal surface side, and the oxide film surface becomes phosphorus feet. This prevents the growth of a uniform oxide film, and as the oxide film grows, the original substrate surface is incorporated into the oxide film, resulting in an oxide film with a small interface state density. Since the oxide film is placed in a pBN container and sealed in the ampoule, the amount of impurities mixed into the oxide film produced is extremely low compared to when the oxide film is placed directly in the ampoule, which improves the characteristics of devices using this oxide film. It has the effect of being able to improve the

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明に係る酸化膜形成装置の構成例を示す断
面図、 第2図(a)はそれに用いられるpBN製容器の断面正
面図、 第2図(b)はそのB−B’線に沿った断面側面図、 第3図は本発明の実施例を適用して得られるMOSキャ
パシタの容量−電圧特性を示すグラフ、第4図(a)は
本発明の実施例を適用して得られる酸化膜中の不純物量
の深さ方向の分布を示すグラフ、 第4図(b)はpBN容器を使用しないで形成された酸
化膜中の不純物量の深さ方向分布を示すグラフである。 1・・・・pBN製容器、2・・・・石英アンプル、4
・・・・支持台、5・・・・ウェーハ。 第1図 第2図 (0)        (b) 日 5  く− 、べ            \1゜ ・   IC 第4 女品力\らがアゴ(nm) (b) 表面っ、らの1で(nm) 平成 2年11月 7日
FIG. 1 is a sectional view showing a configuration example of an oxide film forming apparatus according to the present invention, FIG. 2(a) is a sectional front view of a pBN container used therein, and FIG. 2(b) is a sectional view taken along line BB'. 3 is a graph showing the capacitance-voltage characteristics of a MOS capacitor obtained by applying the embodiment of the present invention, and FIG. 4(a) is a cross-sectional side view taken along the line. A graph showing the distribution of the amount of impurities in the depth direction in the obtained oxide film. FIG. 4(b) is a graph showing the distribution in the depth direction of the amount of impurities in the oxide film formed without using a pBN container. . 1... pBN container, 2... quartz ampoule, 4
...Support stand, 5...Wafer. Figure 1 Figure 2 (0) (b) Day 5 Ku-,be \1゜・IC 4 Woman's grace \Raga chin (nm) (b) Surface ra no 1 (nm) Heisei 2 November 7th

Claims (1)

【特許請求の範囲】[Claims] (1)化合物半導体基板上に酸化膜を形成するにあたり
、半密閉型のpBN製容器に入れた上記化合物半導体基
板を化合物半導体基板の構成元素のうち蒸気圧の高い元
素とともに石英製アンプル中に挿入して、該アンプル内
を真空にしてから酸素ガスを導入したのちアンプルを封
止し、このアンプルを加熱して上記化合物半導体基板上
に酸化膜を形成するようにしたことを特徴とする化合物
半導体表面の酸化膜形成方法。
(1) When forming an oxide film on a compound semiconductor substrate, the above compound semiconductor substrate placed in a semi-closed pBN container is inserted into a quartz ampoule together with an element having a high vapor pressure among the constituent elements of the compound semiconductor substrate. A compound semiconductor characterized in that the ampoule is evacuated, oxygen gas is introduced, the ampoule is sealed, and the ampoule is heated to form an oxide film on the compound semiconductor substrate. Method of forming an oxide film on the surface.
JP22397090A 1990-08-24 1990-08-24 Formation of oxide film on the surface of compound semiconductor Pending JPH04106928A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22397090A JPH04106928A (en) 1990-08-24 1990-08-24 Formation of oxide film on the surface of compound semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22397090A JPH04106928A (en) 1990-08-24 1990-08-24 Formation of oxide film on the surface of compound semiconductor

Publications (1)

Publication Number Publication Date
JPH04106928A true JPH04106928A (en) 1992-04-08

Family

ID=16806536

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22397090A Pending JPH04106928A (en) 1990-08-24 1990-08-24 Formation of oxide film on the surface of compound semiconductor

Country Status (1)

Country Link
JP (1) JPH04106928A (en)

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