JPH04106935A - Dual direction thyristor - Google Patents

Dual direction thyristor

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Publication number
JPH04106935A
JPH04106935A JP22471990A JP22471990A JPH04106935A JP H04106935 A JPH04106935 A JP H04106935A JP 22471990 A JP22471990 A JP 22471990A JP 22471990 A JP22471990 A JP 22471990A JP H04106935 A JPH04106935 A JP H04106935A
Authority
JP
Japan
Prior art keywords
capacitance
layer
base
voltage
punch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP22471990A
Other languages
Japanese (ja)
Other versions
JPH0685438B2 (en
Inventor
Koichi Ota
太田 鋼一
Susumu Yoshida
進 吉田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shindengen Electric Manufacturing Co Ltd
Original Assignee
Shindengen Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shindengen Electric Manufacturing Co Ltd filed Critical Shindengen Electric Manufacturing Co Ltd
Priority to JP2224719A priority Critical patent/JPH0685438B2/en
Publication of JPH04106935A publication Critical patent/JPH04106935A/en
Publication of JPH0685438B2 publication Critical patent/JPH0685438B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Thyristors (AREA)

Abstract

PURPOSE:To make it possible to manufacture a low pressure resistance and low capacitance device easily by further reducing punch-through voltage so that it is smaller than PN junction pressure resistance between a P (n)-type common substrate semiconductor and an N (p)-type base. CONSTITUTION:P<+> regions C and C' are installed on an exposed portion on the surface of a P-type substrate. This region is so formed that the punch-through voltage determined by a span 1 between an N1 base and N2 base is lower than an avalanche yield voltage of junctions J2 and J3. The breakdown strength of a device is determined by the impurity concentration of a P layer and a span 1 between punch-through portions C and C' and an N base. The breakdown strength is determined only by the span l in the case of the same impurity concentration. Therefore, a required lower breakdown strength is available by the selection of a thickness l. The capacitance of the device can be determined by the concentration of impurities. However, the thickness of the P layer portion which excludes the C and C' portions related with the capacitance value is greater while the concentration of impurities is smaller, which makes it possible to minimize the capacitance. It is, therefore, possible to obtain a dual directional thyristor characteristic of lower breakdown strength and a smaller capacitance as well.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明はPNPNP (NPNPN)両方向サイリスタ
、特に耐圧(Vao)の低圧化と静電容量の低減化に関
するものである。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a PNPNP (NPNPN) bidirectional thyristor, particularly to lowering the breakdown voltage (Vao) and reducing the capacitance.

(従来の技術) 第1図(a)に示す如き基本構造をもつ両方向サイリス
タ、即ちP型半導体基板の両面にN1層とN2層を形成
し、更にNl、N2層中の一部に表面に露呈するP、、
22層を形成して、金属電極T IIT2により前記2
1層とN1層及び22層とN2層をそれぞれ短絡した構
造の5層構造をもち、以下のように動作する両方向サイ
リスタはよく知られている。
(Prior art) A bidirectional thyristor having the basic structure as shown in FIG. The exposed P...
22 layers are formed, and the metal electrode T IIT2
A bidirectional thyristor is well known, which has a five-layer structure in which the first layer and the N1 layer and the 22nd layer and the N2 layer are short-circuited, respectively, and operates as follows.

第1図(a)の拡散断面図中に示す矢印方向の電流を流
す方向の電圧が印加されるものとする。この電圧が接合
J3の耐圧(V、。)を超えると接合J3を通って電流
が流れ出す。するとこの電流のうちN2層を横方向に流
れる電流成分I2と、横方向抵抗Rにもとづく電圧降下
か接合J、を順バイアスして22層より正孔の注入を生
しさせる。このため第1図(blに示す電圧電流特性図
のように電極T、、T2間をターンオンさせる。
It is assumed that a voltage is applied in a direction that causes a current to flow in the direction of the arrow shown in the diffusion cross-sectional view of FIG. 1(a). When this voltage exceeds the withstand voltage (V, .) of junction J3, current begins to flow through junction J3. Then, the current component I2 flowing laterally through the N2 layer of this current and the voltage drop based on the lateral resistance R or the junction J are forward biased to cause holes to be injected from the 22nd layer. For this purpose, the electrodes T, T2 are turned on as shown in the voltage-current characteristic diagram shown in FIG.

また前記と逆方向の電圧か印加されたときは、N1層を
横方向に流れる電流成分によって接合J1を順バイアス
して、第1図18+のように電極T1゜72間をターン
オンさせてスイッチング動作を行う。
When a voltage in the opposite direction to the above is applied, the junction J1 is forward biased by the current component flowing in the lateral direction in the N1 layer, turning on the electrode T1°72 as shown in FIG. I do.

この両方向サイリスタは2端子てあって使用か簡単であ
り、しかも小型軽量であるため、弱電回路例えば通信回
線に接続された各種電子回路のサージ防護用素子として
広く使用されるようになりつつある。
Since this bidirectional thyristor has two terminals and is easy to use, and is also small and lightweight, it is becoming widely used as a surge protection element for various electronic circuits connected to low-power circuits, such as communication lines.

しかし最近のように電子回路の集積化が進んでその耐電
圧値が低くなるに伴い、両方向サイリスタとして低耐圧
(V、、)のものへの要求が強くなり、また最近のデジ
タル化の進展は静電容量の小さい素子への要求を強めつ
つある。
However, as electronic circuits have recently become more integrated and their withstand voltages have become lower, there has been a strong demand for bidirectional thyristors with low withstand voltages (V,...), and the recent progress in digitalization has increased. Demand for elements with low capacitance is increasing.

(従来技術とその問題点) しかしこのようなアバランシェ降伏による従来の両方向
サイリスクの構造では、第1図18+のT。
(Prior art and its problems) However, in the conventional bidirectional cross-risk structure based on such avalanche breakdown, T of 18+ in FIG.

72間の耐圧V B OはP層の比抵抗、即ち不純物濃
度によりほぼ一義的にきまり、不純物濃度か小さくなる
とvaoは高くなる。
The breakdown voltage V B O between 72 and 72 is almost uniquely determined by the specific resistance of the P layer, that is, the impurity concentration, and as the impurity concentration decreases, vao increases.

一方素子の静電容量を決定する接合J2.J3の静電容
量は、P層の不純物濃度によってほぼ一義的に定まり、
よく知られるように不純物濃度か小になるとこれに比例
して静電容量も小になる。
On the other hand, the junction J2 which determines the capacitance of the element. The capacitance of J3 is almost uniquely determined by the impurity concentration of the P layer,
As is well known, as the impurity concentration decreases, the capacitance decreases in proportion.

従って耐圧を低くするためP層の不純物濃度を高くする
と静電容量も大きくなる、所謂トし一ドオフの関係とな
るので、低耐圧で低静電容量の両方向サイリスタの実現
は難しい。
Therefore, if the impurity concentration of the P layer is increased in order to lower the breakdown voltage, the capacitance also increases, resulting in a so-called one-doff relationship, making it difficult to realize a bidirectional thyristor with low breakdown voltage and low capacitance.

そこでこれを解決する手段として、第1図(a)のP層
の厚みW、をtJ)とすることにより不純物濃度を犬と
して、耐圧VBOを従来のように接合J2゜J3のアバ
ランシェ降伏によることなく、N、 PN2層のパンチ
スルーによって得るようにする方法か考えられる。
Therefore, as a means to solve this problem, the thickness W of the P layer shown in FIG. Instead, it may be possible to obtain it by punching through two layers of N and PN.

しかしこの方法によって所要の低耐圧かつ低静電容量の
素子を得ようとすると、第1図(a)のP層の厚みW、
か薄くなり過ぎるため製造か困難となり、実現か難しい
However, when trying to obtain a device with the required low breakdown voltage and low capacitance using this method, the thickness W of the P layer in FIG. 1(a),
However, it becomes too thin and difficult to manufacture, making it difficult to realize it.

例えばP層の不純物濃度を1014/cc、 N+ 、
 N=層の表面濃度を10”/cc、その拡散深さを3
0μとし、不純物分布を誤差関数型を仮定してパンチス
ルー電圧を150Vにすると、P層への空乏層の拡がり
、従ってN、、N2層におけるP層の厚みW、は35μ
程度となる。その結果N、、N2層を含めた素子全体の
厚さは100μ程度となるので、現在よく使用されてい
る4吋ウェハなとを用いての製造処理には著しい困難を
生ずる。
For example, if the impurity concentration of the P layer is 1014/cc, N+,
N = layer surface concentration 10”/cc, its diffusion depth 3
0μ, assuming the impurity distribution to be an error function type, and setting the punch-through voltage to 150V, the spread of the depletion layer to the P layer, and therefore the thickness W of the P layer in the N2 layer, is 35μ.
It will be about. As a result, the thickness of the entire device including the N, N2 layers is approximately 100 μm, which poses significant difficulties in manufacturing using 4-inch wafers, which are commonly used at present.

(発明の目的) 本発明は前記パンチスルーによる手段を利用して通常の
選択拡散等の公知の手段により、所要の低耐圧かつ低静
電容量の素子を容易に製造しうる構造を提供し、前記デ
ジタル化処理機能をもった集積回路などこの種回路のサ
ージ防護を確実に行いうる両方向サイリスタの実現を図
ったものである。
(Objective of the Invention) The present invention provides a structure in which an element with a required low breakdown voltage and low capacitance can be easily manufactured by a known means such as ordinary selective diffusion using the punch-through method, The present invention aims to realize a bidirectional thyristor that can reliably provide surge protection for this type of circuit, such as the integrated circuit having the digitalization processing function.

(問題点を解決するための本発明の手段)本発明の特徴
とするところは、5層構造をもつ両方向サイリスタのP
、NF2 (N、PN2)層の一部に、その耐圧かパン
チスルーによって決まる領域を設けることにより、P層
の主体部分の厚み、従って素子の厚みをアバランシェ降
伏による従来素子と同様としたまま、低耐圧の素子を実
現できるようにして、要求される低耐圧と低静電容量の
素子を容易に製造できるようにしたものである。次に本
発明を一実施例により説明する。
(Means of the present invention for solving the problems) The present invention is characterized by a bidirectional thyristor having a five-layer structure.
By providing a region determined by its breakdown voltage or punch-through in a part of the NF2 (N, PN2) layer, the thickness of the main portion of the P layer, and therefore the thickness of the device, can be maintained the same as that of conventional devices due to avalanche breakdown. This makes it possible to realize an element with a low breakdown voltage, thereby making it possible to easily manufacture an element with the required low breakdown voltage and low capacitance. Next, the present invention will be explained by way of an example.

(実施例) 第2図(a)(b)(c)は本発明の一実施例を示す平
面図、平面図のA−A’部矢視拡散断面図及びその等価
回路図である。本発明はP型基板の表面に露出する部分
にP゛領域c、  c’ を設け、この領域をN、、N
2ベース間との距離βによってきまるパンチスルー電圧
か、接合J2.J3のアバランシェ降服電圧より低くな
るようにしたものである。
(Embodiment) FIGS. 2(a), 2(b), and 2(c) are a plan view showing an embodiment of the present invention, a diffusion cross-sectional view taken along line A-A' in the plan view, and an equivalent circuit diagram thereof. In the present invention, P' regions c and c' are provided on the exposed surface of the P-type substrate, and these regions are N, , N
The punch-through voltage determined by the distance β between the two bases or the junction J2. It is designed to be lower than the avalanche breakdown voltage of J3.

次にその動作について説明する。Next, its operation will be explained.

令弟2図(b)図中の矢印方向の電流を流す極性で電圧
が印加されたものとする。すると印加電圧か距離rに相
当するパンチスルー電圧に達するとCを通して電流Iか
流れ出す。電流Iか増加すると、22層直下のN2@の
実効横方向抵抗Rによる電圧降下により接合J4を順バ
イアスするため、領域Cに近い部分J4て22層より正
孔の注入か行われる。このことは第2図Klで主サイリ
スタN1PN2P、のN2.PCパンチスルーダイオー
ド)に、点弧電流Iか流出入することに相当するから、
主サイリスタはこの近傍からターンオンを開始し、全面
にターンオン領域か拡がることになる。上記の動作は構
造か対称であるから、以上と電圧の印加方向か逆の場合
においてもC′細部分より同一の動作か行われる。
It is assumed that a voltage is applied with a polarity that causes a current to flow in the direction of the arrow in Figure 2 (b). Then, when the applied voltage reaches a punch-through voltage corresponding to the distance r, a current I begins to flow through C. When the current I increases, the junction J4 is forward biased due to the voltage drop due to the effective lateral resistance R of N2@ directly under the 22nd layer, so holes are injected from the 22nd layer in the portion J4 near the region C. This can be seen in the main thyristor N1PN2P, N2. This corresponds to the ignition current I flowing in and out of the PC punch-through diode.
The main thyristor starts turning on from this vicinity, and the turn-on region spreads over the entire surface. Since the above operation is symmetrical in structure, the same operation is performed from the C' detail even when the voltage is applied in the opposite direction.

以上のように本発明素子の耐圧V8oはP層の不純物濃
度とパンチスル一部分c、 c’  とNベースの距離
lて決まり、同一不純物濃度ではlのみて決まるため、
厚みlの選定によって所望の低耐圧化か可能となる。
As described above, the breakdown voltage V8o of the device of the present invention is determined by the impurity concentration of the P layer and the distance l between the punch holes c and c' and the N base, and for the same impurity concentration, it is determined only by l,
By selecting the thickness l, it is possible to achieve a desired low breakdown voltage.

また素子の静電容量、従って接合J2.J3の静電容量
は不純物濃度のみによって決まるか、静電容量値に関係
するC2C“部分以外のP層部分、従ってP層の主体部
分の厚みは大であって不純物濃度は小であるので、静電
容量を小にすることかてき、前記トレードオフの問題は
一挙に解決されて低耐圧であって静電容量の小さい両方
向サイリスタの提供か可能となる。
Also, the capacitance of the element and hence the junction J2. The capacitance of J3 is determined only by the impurity concentration, or the thickness of the P layer portion other than the C2C portion related to the capacitance value, and therefore the main portion of the P layer, is large and the impurity concentration is small. By reducing the capacitance, the trade-off problem described above is solved at once, and it becomes possible to provide a bidirectional thyristor with low breakdown voltage and small capacitance.

また本発明てはパンチスル一部分c、  c’以外のP
層部分、即ちP層の主体部分の厚みを従来のアバランシ
ェ降伏による素子と同様に厚くでき、素子そのものの厚
みを大にてきる。従って前記したP層全体の厚みを薄く
することによってパンチスルー構造を得るものに比へて
、製造処理上の困難を著しく少なくてきる。
In addition, in the present invention, the punch sle part c, P other than c'
The thickness of the layer portion, that is, the main portion of the P layer, can be made as thick as in the conventional device based on avalanche breakdown, and the thickness of the device itself can be increased. Therefore, the difficulties in manufacturing process are significantly reduced compared to the case where a punch-through structure is obtained by reducing the overall thickness of the P layer described above.

これに加えて本発明によれば、サージ防護に当たって要
求される性能であるサージ電流耐量のはらつきの少ない
素子をうることかできる。即ちサージ電流耐量は第1図
(blに示すターンオン移行領域における電力損失と、
最初にタン−オンする位置即ち初期点弧位置からの全面
へのターンオン領域の拡がり速度に大きく影響される。
In addition, according to the present invention, it is possible to obtain an element with less variation in surge current withstand capacity, which is a performance required for surge protection. In other words, the surge current withstand capacity is determined by the power loss in the turn-on transition region shown in Figure 1 (bl),
It is greatly influenced by the speed at which the turn-on area spreads over the entire surface from the initial turn-on position, that is, the initial ignition position.

しかし従来の素子では点弧位置か一定しないため、サー
ジ電流耐量にばらつきを生じ易い。
However, in conventional elements, the ignition position is not constant, which tends to cause variations in surge current withstand capacity.

しかし本発明では初期点弧位置はパンチスルー部分c、
c’ に必ず局限されるため、サージ電流耐量のほらつ
きの殆どない両方向サイリスタの提供か可能となる。
However, in the present invention, the initial firing position is the punch-through portion c,
Since the current is always localized to c', it is possible to provide a bidirectional thyristor with almost no variation in surge current resistance.

以上本発明の一実施例について説明したか、第3図(a
l (blに示す平面図、および拡散断面図のものは、
通常用いられるチャンネルストッパーC8を利用して、
Nベース層との距離を一部分小さ(することにより、パ
ンチスルー領域を形成した実施例である。また本発明の
実施例においては、パンチスルーを行わせるためのP+
領域をP基板の表面露出部分に設けたか、埋込拡散等に
よって内部に設けることも可能であり、種々の変形か可
能である。例えば表面側から見てリング状に連結して設
けたり、点状に不連続に設けることかできる。
One embodiment of the present invention has been described above, and FIG.
l (The plan view and diffusion cross-sectional view shown in bl are
Using the commonly used channel stopper C8,
This is an embodiment in which a punch-through region is formed by partially reducing the distance to the N base layer.In addition, in the embodiment of the present invention, the P+
It is possible to provide the region on the exposed surface portion of the P substrate or to provide it inside by buried diffusion, etc., and various modifications are possible. For example, when viewed from the surface side, they may be connected in a ring shape or discontinuously provided in a dotted manner.

また製造方法も公知の種々のものを用いることも可能で
ある。また更に本発明はPNPNP (NPNPN)両
方向サイリスタを基本構造とする複合サイリスタに適用
して効果を挙げることかできる。
Furthermore, various known manufacturing methods can also be used. Furthermore, the present invention can be effectively applied to a composite thyristor whose basic structure is a PNPNP (NPNPN) bidirectional thyristor.

(発明の効果) 以上の説明から明らかなように本発明によれは、低耐圧
であって静電容量か小さく、しかもサージ電流耐量のば
らつきの少ないデジタル信号を扱う集積回路のサージ防
護に好適する両方向サイリスタを提供できる。
(Effects of the Invention) As is clear from the above description, the present invention is suitable for surge protection of integrated circuits that handle digital signals that have low withstand voltage, small capacitance, and less variation in surge current withstand capacity. Bidirectional thyristors can be provided.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来素子の説明図、第2図は本発明の一実施例
の説明図、第3図は本発明の他の実施例の説明図である
FIG. 1 is an explanatory diagram of a conventional element, FIG. 2 is an explanatory diagram of one embodiment of the present invention, and FIG. 3 is an explanatory diagram of another embodiment of the present invention.

Claims (2)

【特許請求の範囲】[Claims] (1)共通基板半導体P(N)型の両面にそれぞれN(
P)ベース及びP(N)ベースを設け、各面のN(P)
ベースの一部を表面に露呈させてP(N)エミッタと短
絡して一つの電極を構成してなり、かつ前記共通基板半
導体に同一伝導型の不純物領域P^+(N^+)を設け
、このP^+(N^+)領域とN(P)ベース間の距離
によって定まるパンチスルー電圧をP(N)型共通基板
半導体とN(P)型ベース間のPN接合の耐圧より小と
したことを特徴とする両方向サイリスタ。
(1) Both sides of the common substrate semiconductor P(N) type have N(
P) base and P(N) base are provided, and N(P) of each surface is
A part of the base is exposed on the surface and short-circuited with the P(N) emitter to form one electrode, and an impurity region P^+ (N^+) of the same conductivity type is provided in the common substrate semiconductor. , the punch-through voltage determined by the distance between this P^+(N^+) region and the N(P) base is set to be smaller than the breakdown voltage of the PN junction between the P(N) type common substrate semiconductor and the N(P) type base. A bidirectional thyristor characterized by:
(2)P^+(N^+)領域をP(N)型基板の表面に
露出した部分に設けたことを特徴とする特許請求の範囲
第1項記載の両方向サイリスタ。
(2) The bidirectional thyristor according to claim 1, wherein the P^+(N^+) region is provided in a portion exposed on the surface of the P(N) type substrate.
JP2224719A 1990-08-27 1990-08-27 Bidirectional thyristor Expired - Fee Related JPH0685438B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2224719A JPH0685438B2 (en) 1990-08-27 1990-08-27 Bidirectional thyristor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2224719A JPH0685438B2 (en) 1990-08-27 1990-08-27 Bidirectional thyristor

Publications (2)

Publication Number Publication Date
JPH04106935A true JPH04106935A (en) 1992-04-08
JPH0685438B2 JPH0685438B2 (en) 1994-10-26

Family

ID=16818178

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2224719A Expired - Fee Related JPH0685438B2 (en) 1990-08-27 1990-08-27 Bidirectional thyristor

Country Status (1)

Country Link
JP (1) JPH0685438B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011014613A (en) * 2009-06-30 2011-01-20 Sanken Electric Co Ltd Semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01307264A (en) * 1988-06-06 1989-12-12 Nippon Telegr & Teleph Corp <Ntt> Pnpn surge-preventing device
JPH01307265A (en) * 1988-06-06 1989-12-12 Nippon Telegr & Teleph Corp <Ntt> Pnpn surge-preventing device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01307264A (en) * 1988-06-06 1989-12-12 Nippon Telegr & Teleph Corp <Ntt> Pnpn surge-preventing device
JPH01307265A (en) * 1988-06-06 1989-12-12 Nippon Telegr & Teleph Corp <Ntt> Pnpn surge-preventing device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011014613A (en) * 2009-06-30 2011-01-20 Sanken Electric Co Ltd Semiconductor device

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JPH0685438B2 (en) 1994-10-26

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