JPH04106973A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To make it possible to draw a plurality of metallic wiring layers from pointers of a semiconductor integrated circuit device by regularly laying out a plurality of metallic wiring layers and the pointers having electrically connected metallic layers in the semiconductor integrated circuit device. CONSTITUTION:Pointers comprising a through hole 1, a metallic layer 2 connected to the first metallic wiring layer, and a metallic layer 3 connected to the 2nd... and the nth metallic wiring layers are regularly laid out, for example, on both sides of a transistor region 5 where unit cells are extended. Further, reference number 6 represents a semiconductor chip. Since the pointers are thus laid out regularly that comprises through holes and the metallic layers each electrically connected to each corresponding one of a plurality of metallic wiring layers, wiring of these pointers makes it possible to connect themselves to a plurality of metallic layers without considering wiring of each metallic wiring layer.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device using a master slice method, and in particular to a semiconductor integrated circuit device that eliminates the need to consider wiring for each of a plurality of metal wiring layers at input/output terminals. Related to circuit devices.

[Prior Art] Conventionally, a master slicing method has been adopted to efficiently manufacture semiconductor integrated circuit devices of a wide variety in small quantities. This master slicing method involves creating a large number of unit cells in a lattice pattern in advance on one semiconductor wafer, creating a wiring mask according to the product to be developed, and connecting the unit cells to achieve the desired electrical This realizes an integrated circuit device having circuit operation.

Conventionally, the structure of a unit cell used in this master slice method has generally been composed of two sets of complementary transistors, as described in, for example, Japanese Unexamined Patent Publication No. 54-93375. be. In other words, as shown in the seventh diagram, the unit cell consists of two P-M
OS) transistors TRt, TR2 and two N-MOS
) transistors TR3 and TR4, and transistors having the same channel share one of their sources or drains, and two sets of transistors having different channels share a gate.

FIG. 7(B) is a diagram showing an impurity implantation region pattern and a gate electrode pattern for realizing the circuit configuration of a Uni7) cell, where 101 is a first gate electrode layer made of polysilicon;
10IA, 10IB, and 10IC are first gate input terminal outlets; 102 is a second gate electrode layer made of polysilicon; 102A, 102B.

102C is a second gate input terminal outlet.

Also, 103.104.105 is an N-type region, N-MO
It constitutes the source and drain regions of the S transistor, and 106, 107, and 108 are P-type regions, P-
MOS) constitutes the source and drain regions of transistors. Reference numeral 109 denotes a P-well region in which the N-MO3) transistor is formed, and is previously formed on the N-type silicon substrate 110. Then, automatic placement and wiring is performed for the unit cells configured in this manner using a CAD system to realize a desired integrated circuit device.

(Problem to be Solved by the Invention) However, when automatically placing and wiring a unit cell using a CAD system, input/output signals to the unit cell formed by the transistor Mvi are transmitted through multiple metal wiring layers from the input/output terminal. In the CAD system, the connection information for each input/output terminal must be registered separately for each metal wiring layer, which is a problem in that the burden on the designer cannot be reduced. was there.

The present invention has been made to solve the above-mentioned problems in semiconductor integrated circuit devices using the conventional master slice method. It is an object of the present invention to provide a semiconductor integrated circuit device that can significantly reduce the burden.

[Means and effects for solving the problem] In order to solve the above problems, in a master slice type semiconductor integrated circuit device comprising a large number of unit cells and a plurality of metal wiring layers, through-holes and the plurality of metal wiring layers are provided. Pointers made of a plurality of metal layers each connected to a wiring layer and oversized in the through hole are regularly arranged.

That is, as shown in FIG. 1, a through hole I, a metal layer 2 connected to a first metal wiring layer oversized to this through hole 1, and a second, . . . , nth metal As shown in FIG. 2, a struture (referred to as a pointer) 4 composed of a metal layer 3 connected to a wiring layer is connected to a tilted wall 5 of a transistor constituting a unit cell, for example.
They are arranged regularly on both sides of the Note that in FIG. 2, 6 is a semiconductor integrated circuit chip.

In this way, the pointers made up of through holes and metal layers electrically connected to multiple metal wiring layers are arranged regularly, so by wiring between these pointers, it is possible to connect to multiple metal wiring layers. This eliminates the need to consider wiring for each metal wiring layer.

〔Example〕

Next, an example will be described. FIG. 3 is a diagram showing the configuration of a unit cell portion of an embodiment of the semiconductor integrated circuit device according to the present invention. When performing automatic placement and routing, tracks for routing are required, but in this example, 6 tracks in the vertical direction are required.
Trunk■2001. (2) constitutes one unit cell, which becomes the master bulk. In FIG. 3, II is a gate electrode made of polysilicon, 12 is an outlet of the gate electrode 11, 13 is a P diffusion region,
This constitutes the source/drain region of the P-MOS transistor. Reference numeral 14 denotes an outlet of the P'' diffusion region 13, 15 an N'' type diffusion region, which constitutes the source/drain region of the N-MOS transistor;
Reference numeral 6 denotes an outlet for the N'' type diffusion H region 15. Also 1
7 is a power supply wiring, 18 is a ground wiring, 19 is an N-well region, 20 is an N-well potential extraction port, 21 is a P-type substrate,
22 is a potential extraction port of the P-type substrate 21. The pointer 4 having the configuration shown in FIG. 1 is placed above and below the positions of odd-numbered tracks (2), (2), and (3) as shown.

Using the unit cell configured in this way, the logic non-pole is shown in diagram 4, and the circuit configuration is shown in diagram 4 fBl.
When configuring a human-powered NAND circuit, a layout as shown in FIG. 5 is applied, and the first and second metal wiring layers 29
．． form 30. In addition, in 4th Kaida) and FIG. 5, 25.26 shows a P-M*S transistor, and 27.28 shows an N-MOS l-transistor.

Since the pointer 4 is electrically connected to a plurality of (two layers in this embodiment) metal wiring layers 29 and 30, the position of the pointer 4 is registered as the input/output terminal position of the unit cell. If this is done, in a CAD system for automatic placement and wiring, there is no need to register connection information separately for each metal wiring layer, and the burden on the designer can be significantly reduced.

Furthermore, even when wiring is performed manually, the desired circuit can be realized by simply connecting the necessary nets between pointers, which greatly reduces layout work.

FIG. 6 is a plan view showing the second embodiment.

In this embodiment, when there is a wiring prohibited area 32 by the first metal wiring layer 31 due to a transistor area, a power supply wiring area, etc. in a unit cell, the wiring prohibited area 32
A unit cell is constructed by placing pointers 4 in advance on both sides of the cell. When it is desired to perform wiring by crossing this wiring prohibited area 32, a second metal wiring layer 33 disposed on the first metal wiring layer 31 is placed between the pointers 4.
Wiring is possible by connecting using .

Since the wiring passing positions are determined in advance by the pointers in this way, when wiring is made using a metal wiring layer that can pass between the necessary pointers during layout, electrical connections can be made and a desired circuit can be realized. Therefore, when a designer wants to perform cross-under wiring, the pointer is placed on the bulk at a position that satisfies the design rules, so they can concentrate only on the wiring without considering the details. This reduces the burden and prevents wiring errors.

[Effects of the Invention] As described above based on the embodiments, according to the present invention, pointers having a metal layer electrically connected to a plurality of metal wiring layers are regularly arranged. By wiring the pointer, multiple metal wiring layers can be drawn out from the pointer.

In addition, by placing the pointer configured in this way at the input/output terminal position of a unit cell composed of a transistor area, connection information for each terminal with multiple metal wiring layers can be obtained for each metal wiring layer during automatic placement and wiring. There is no need to register, which greatly reduces the burden on designers.

[Brief explanation of the drawing]

FIG. 1 is a conceptual diagram showing the configuration of pointers arranged in a semiconductor integrated circuit device according to the present invention, FIG. 2 is a schematic diagram showing an example of the arrangement of pointers on a chip, and FIG.
The fourth diagram, o3) is a plan view of a pattern showing the first embodiment of the present invention, is a logic symbol diagram and circuit configuration diagram of a NAND circuit, and FIG. 5 is a layout diagram when configuring a NAND circuit. The figure is a plan view of a pattern showing the second embodiment, and FIG. In the figure, 1 is a through hole, 2 is a first metal layer, and 3 is a through hole.
is the second. ... nth metal layer, 4 is a pointer, 5
1 is a transistor region, 6 is a tin tube, 11 is a gate electrode, 12 is a gate electrode outlet, 13 is a P dispersion region,
14 is a P゛ diffusion area number outlet, 15 is a N゛ diffusion area,
16 is the N-wide diffusion receiving outlet, 17 is the power supply wiring, and 18 is the
19 is a ground wiring, 19 is an N-well region, 20 is an N-well potential extraction port, 21 is a P-type substrate, and 22 is a P-type substrate potential extraction port. Patent Applicant Olympus Optical Industry Co., Ltd. 4, Poi, Yuto and Figure 2 6: Chinov 31゛First metal wiring layer 32 Wiring prohibited area of the first metal wiring layer 33: Second metal wiring layer

Claims (1)

[Claims] 1. In a master slice type semiconductor integrated circuit device comprising a large number of unit cells and a plurality of metal wiring layers,
1. A semiconductor integrated circuit device, characterized in that pointers each including a through hole and a plurality of metal layers each connected to the plurality of metal wiring layers and oversized to the through hole are regularly arranged. 2. The semiconductor integrated circuit device according to claim 1, wherein the pointers are arranged at input/output terminal positions of the unit cell on both sides of a transistor region constituting the unit cell.