JPH04106975A - Manufacture of solid state image sensor - Google Patents

Manufacture of solid state image sensor

Info

Publication number
JPH04106975A
JPH04106975A JP2224608A JP22460890A JPH04106975A JP H04106975 A JPH04106975 A JP H04106975A JP 2224608 A JP2224608 A JP 2224608A JP 22460890 A JP22460890 A JP 22460890A JP H04106975 A JPH04106975 A JP H04106975A
Authority
JP
Japan
Prior art keywords
charge transfer
sidewall
region
conductivity type
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2224608A
Other languages
Japanese (ja)
Inventor
Hisao Kawaura
久雄 川浦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2224608A priority Critical patent/JPH04106975A/en
Publication of JPH04106975A publication Critical patent/JPH04106975A/en
Pending legal-status Critical Current

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  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

PURPOSE:To suppress irregularities in various characteristics such as a dark current, a light signal storage capacity, an after image, etc., for a solid state image sensor by providing a sidewall at the side of a charge transfer electrode, then ion implanting it, and forming a buried photodiode region. CONSTITUTION:Sidewalls 12-1, 12-2 are formed on the side of a charge transfer electrode 7 through a silicon oxide film 14 by anisotropically etching. Then, with the electrode 7 and the sidewalls 12-1, 12-2 as masks P-type impurity such as boron is ion implanted about 10<13>/cm<2> to form a P<+> type semiconductor layer 10a in a self-alignment manner. Since the width of the sidewall is reduced smoothly upward, an impurity concentration profile of the layer 10a has a trend for reducing toward the electrode 7 in the vicinity directly under the sidewall. Then, the sidewall is removed by wet etching, and a buried photodiode region 8'b can be formed with high reproducibility.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は固体撮像装置の製造方法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a solid-state imaging device.

〔従来の技術〕[Conventional technology]

第3図(a)〜(d)は、縦型オーバフロードレイン構
造、埋込みホトタイオートを有するCCD型の固体撮像
装置の製造方法の従来例を説明するための工程順に配置
した半導体チップの断面図である。
FIGS. 3(a) to 3(d) are cross-sectional views of semiconductor chips arranged in the order of steps for explaining a conventional method for manufacturing a CCD type solid-state imaging device having a vertical overflow drain structure and an embedded photodiode. .

まず、第3図(a)に示すように、単結晶Siからなる
N型半導体基板1の表面部にドース量1o12/cm2
程度のP型ウェル2を形成し、P+型チャネルストッパ
4(ドース量1013/cm2程度)を形成して素子分
離を行ない、N型の電荷転送領域3(ドーズ量1o12
/cm2程度)を形成し、電荷転送パルスを加える電極
となる300nm膜厚のリンドープされたポリシリコン
膜からなる電荷転送電極7を形成する 次に第3図(b
)に示すように、電荷転送電極7及びその表面の酸化シ
リコン膜をマスクにしてN型不純′S(例えばリン)を
ドーズ量I Q 12′c m”程度イオン注入し、光
信号蓄積部にあたるN−型のホトダイオ−1−領域8を
形成する、 次に第3図(c)に示すように、ホトレジスト膜9をマ
スクにしてP型不純物(例えばホロン)をイオン注入し
、浅くP+型半導体層10を形成し、第3図(d)に示
すように、ホトレジスト膜9を剥離する。
First, as shown in FIG. 3(a), a dose of 1o12/cm2 is applied to the surface of an N-type semiconductor substrate 1 made of single crystal Si.
A P-type well 2 of approximately 10 cm is formed, a P+ type channel stopper 4 (dose of approximately 1013/cm2) is formed to perform device isolation, and an N-type charge transfer region 3 (dose of approximately 1013/cm2) is formed.
/cm2), and a charge transfer electrode 7 made of a phosphorus-doped polysilicon film with a thickness of 300 nm, which serves as an electrode for applying a charge transfer pulse, is formed. Next, as shown in FIG.
), using the charge transfer electrode 7 and the silicon oxide film on its surface as a mask, N-type impurity 'S (for example, phosphorus) is ion-implanted at a dose of IQ 12'cm'' to form the optical signal storage area. Form an N- type photodiode region 8. Next, as shown in FIG. 3(c), a P-type impurity (for example, holon) is ion-implanted using the photoresist film 9 as a mask to form a shallow P+-type semiconductor. After forming the layer 10, the photoresist film 9 is peeled off as shown in FIG. 3(d).

一発明か解決しようとする課題〕 上述した従来の固体撮像装置の製造方法によると、P゛
型型厚導体層10ホトレジスト膜をマスクにしてイオン
注入により形成するため、埋込みホトダイオード領域8
′ のうち、表面にP°型型半体体層10形成されてい
ない領域の面積は、ホトレジスト膜の目合せ工程でのず
れにより工程毎にばらついてしまう可能性が大きい。こ
のため暗電流、光信号蓄積容量の残像などの緒特性のは
らつきかさけられないという欠点かある、5課題を解決
するための手段ミ 本発明は、第1導電型半導体基板の表面部に設けられた
第2導電型ウェルに第2導電型チャ本ルストッパて光電
変換領域及び電荷転送領域3区両し、前記電荷転送領域
上にゲート絶縁膜を介して電荷転送電極を形成し、前記
光電変換領域に表面か前記電荷転送領域近傍を除き第2
導電型半導体層で覆われた第1導電型の埋込みホトダイ
オード領域を形成する固体撮像装置の製造方法において
、前記第2導電型半導体層を前記電荷転送電極と自己整
合して形成するというものである。
[Problems to be Solved by the Invention] According to the above-described conventional method for manufacturing a solid-state imaging device, since the P-type thick conductor layer 10 is formed by ion implantation using a photoresist film as a mask, the buried photodiode region 8
′, the area of the region where the P° type half body layer 10 is not formed on the surface is likely to vary from process to process due to misalignment in the alignment process of the photoresist film. For this reason, there is a drawback that variations in the characteristics such as dark current and afterimage of the optical signal storage capacitance cannot be avoided. A second conductivity type challel stopper is provided in the provided second conductivity type well to separate a photoelectric conversion region and a charge transfer region into three sections, a charge transfer electrode is formed on the charge transfer region via a gate insulating film, and a charge transfer electrode is formed on the charge transfer region via a gate insulating film. In the conversion region, the surface or the second region except for the vicinity of the charge transfer region
A method for manufacturing a solid-state imaging device in which a buried photodiode region of a first conductivity type is formed covered with a conductivity type semiconductor layer, wherein the second conductivity type semiconductor layer is formed in self-alignment with the charge transfer electrode. .

〔実施例〕〔Example〕

第1図(a)〜(d)は本発明の第1の実施例を説明す
るための工程順に配置した半導体チップの断面図である
6 従来例において、第3図(a)、(b)を参照して説明
した工程の後に第1図(a)に示すように、ポリシリコ
ン膜11を厚さ400nm程度堆積し、リンドープを行
なった後に、第1図(b)に示すように、巽方性工・ソ
チングを行ない電荷転送電極7の側面に酸化シリコン膜
14を介してサイドウオール12112−2を形成する
、次に、第1図(c)に示すように、電荷転送電極7及
びサイドウオール12−1.12−2をマスクにしてP
型不純S(例えばホロン)を1013cm2程度イオン
注入し自己整合的にP+型半導体層10aを形成する。
FIGS. 1(a) to (d) are cross-sectional views of semiconductor chips arranged in the order of steps for explaining the first embodiment of the present invention.6 In the conventional example, FIGS. 3(a) and (b) After the process described with reference to FIG. 1(a), a polysilicon film 11 is deposited to a thickness of about 400 nm and phosphorus doped, as shown in FIG. 1(b). A sidewall 12112-2 is formed on the side surface of the charge transfer electrode 7 via the silicon oxide film 14 by performing diagonal machining and sawching. Next, as shown in FIG. P using wall 12-1.12-2 as a mask
A P+ type semiconductor layer 10a is formed in a self-aligned manner by ion-implanting type impurity S (for example, holon) to a depth of about 1013 cm2.

サイドウオールの幅がなだらかに上方へ向って小さくな
っているので、P゛型型半体体層10a不純物濃度プロ
ファイルはサイドウオール直下近辺で電荷転送電極7へ
向って減少する傾斜を持つことになる。次に、第1図(
d)に示すように、サイドウオールをウエットエ・ソチ
て除去する。
Since the width of the sidewall gradually decreases upward, the impurity concentration profile of the P'-type half layer 10a has a slope that decreases toward the charge transfer electrode 7 near just below the sidewall. . Next, Figure 1 (
As shown in d), remove the sidewall by wet etching.

サイドウオールの幅はポリシリコン膜11の厚さで決定
されるので高精度に制御でき、再現性よく埋込みホトタ
イオート領域8’  bを形成できる。
Since the width of the sidewall is determined by the thickness of the polysilicon film 11, it can be controlled with high precision, and the buried phototiode region 8'b can be formed with good reproducibility.

第2図(a)〜(c)は本発明の第2の実施例を説明す
るための工程順に示す半導体チップの断面図である。
FIGS. 2(a) to 2(c) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a second embodiment of the present invention.

第1の実施例と同様にサイドウオールを形成した後、第
2図(a)に示すように、電荷転送電極7に付随したサ
イドウオールのうちホトダイオード領域8aから信号を
読出す部分に存在するサイドウオール12−1以外は不
要であるために、ホトレジスト膜13てサイドウオール
12−また(す遮へいし、サイドウオール12−2はウ
ェットエツチングて除去してしまう。次に、第2図(b
)に示すように、電極転送電極7及びサイドウオール1
2−1をマスクにしてP型不純物(例えばホロン)を1
013/cm2程度イオン注入し、自己整合的にP+型
半導体層10bを形成する。次に第2図(C)に示すよ
うに、サイドウオール12−1をウェットエッチして除
去してしまう。この実施例では、サイドウオール12−
2をエツチングしてしまってからイオン注入を行うので
、P+型半導体層10bとP+型チャネルストッパ4の
重なりを十分確保し電気的導通を十分に図れるという利
点がある。
After forming the sidewalls in the same manner as in the first embodiment, as shown in FIG. Since the parts other than the wall 12-1 are unnecessary, the photoresist film 13 is used to shield the side wall 12-1 and the side wall 12-2 is removed by wet etching.Next, as shown in FIG.
), the electrode transfer electrode 7 and the sidewall 1
Using 2-1 as a mask, add a P-type impurity (for example, holon) to 1
Ions are implanted to a depth of about 0.013/cm2 to form a P+ type semiconductor layer 10b in a self-aligned manner. Next, as shown in FIG. 2(C), the sidewall 12-1 is removed by wet etching. In this embodiment, the sidewall 12-
Since the ion implantation is performed after etching the P+ type semiconductor layer 10b and the P+ type channel stopper 4, there is an advantage that sufficient overlap between the P+ type semiconductor layer 10b and the P+ type channel stopper 4 can be ensured and sufficient electrical continuity can be achieved.

3発明の効果] 以上説明したように本発明は、電荷転送電極の側部にサ
イドウオールを設けた後イオン注入を行ないP“型半導
体層を形成して埋込みホトダイオード領域を形成する二
とにより、P+型半導体層は、電荷転送領域に対して自
己整合して形成できるため、量体撮像装置の暗電流、光
信号蓄積容量、残像なとの諸特性のばらつきを抑えるこ
とかできる効果かある。
3 Effects of the Invention] As explained above, the present invention provides the following steps: After providing a sidewall on the side of the charge transfer electrode, ions are implanted to form a P" type semiconductor layer to form a buried photodiode region. Since the P+ type semiconductor layer can be formed in self-alignment with the charge transfer region, it has the effect of suppressing variations in various characteristics such as dark current, optical signal storage capacity, and afterimage of the mass imaging device.

イオード領域、8’ 、8’ a、8′b・・埋込みホ
トダイオード領域、9・ホトレジスト膜、]0]、Oa
、10b・P“型半導体層、11・・ポリシリコン′膜
、12−1.12−2・・サイドウオール、13・・・
ホトレジスト膜、14・・酸化シリコン膜。
Iode region, 8', 8'a, 8'b...Buried photodiode region, 9.Photoresist film, ]0], Oa
, 10b P" type semiconductor layer, 11... polysilicon' film, 12-1.12-2... side wall, 13...
Photoresist film, 14... silicon oxide film.

Claims (1)

【特許請求の範囲】 1、第1導電型半導体基板の表面部に設けられた第2導
電型ウェルに第2導電型チャネルストッパで光電変換領
域及び電荷転送領域を区画し、前記電荷転送領域上にゲ
ート絶縁膜を介して電荷転送電極を形成し、前記光電変
換領域に表面が前記電荷転送領域近傍を除き第2導電型
半導体層で覆われた第1導電型の埋込みホトダイオード
領域を形成する固体撮像装置の製造方法において、前記
第2導電型半導体層を前記電荷転送電極と自己整合して
形成することを特徴とする固体撮像装置の製造方法。 2、電荷転送電極の側面に絶縁膜を介してサイドウォー
ルを形成したのち、前記電荷転送電極及びサイドウォー
ルをマスクにしてイオン注入を行ない第2導電型半導体
層を形成する請求項1記載の固体撮像装置の製造方法。
[Claims] 1. A photoelectric conversion region and a charge transfer region are defined by a second conductivity type channel stopper in a second conductivity type well provided on the surface portion of the first conductivity type semiconductor substrate, and a photoelectric conversion region and a charge transfer region are defined on the charge transfer region. a solid state in which a charge transfer electrode is formed through a gate insulating film, and a buried photodiode region of a first conductivity type whose surface is covered with a semiconductor layer of a second conductivity type except for the vicinity of the charge transfer region is formed in the photoelectric conversion region; A method for manufacturing a solid-state imaging device, characterized in that the second conductivity type semiconductor layer is formed in self-alignment with the charge transfer electrode. 2. The solid according to claim 1, wherein a sidewall is formed on the side surface of the charge transfer electrode via an insulating film, and then ion implantation is performed using the charge transfer electrode and the sidewall as a mask to form the second conductivity type semiconductor layer. A method for manufacturing an imaging device.
JP2224608A 1990-08-27 1990-08-27 Manufacture of solid state image sensor Pending JPH04106975A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2224608A JPH04106975A (en) 1990-08-27 1990-08-27 Manufacture of solid state image sensor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2224608A JPH04106975A (en) 1990-08-27 1990-08-27 Manufacture of solid state image sensor

Publications (1)

Publication Number Publication Date
JPH04106975A true JPH04106975A (en) 1992-04-08

Family

ID=16816395

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2224608A Pending JPH04106975A (en) 1990-08-27 1990-08-27 Manufacture of solid state image sensor

Country Status (1)

Country Link
JP (1) JPH04106975A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08288496A (en) * 1995-04-20 1996-11-01 Nec Corp Solid-state imaging device and method of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08288496A (en) * 1995-04-20 1996-11-01 Nec Corp Solid-state imaging device and method of manufacturing the same

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