JPH04107632A - Information processor - Google Patents

Abstract

PURPOSE:To shorten the access time to the string data with omission of a branch microinstruction by providing a string processing deciding part which decides whether all string data are read through or not. CONSTITUTION:Only '4' equivalent to 4 bytes, for example, which are read out this time is subtracted from the contents of a subtraction counter 5 to which the string data length is set. Then a bus access signal generating part 16 produces and outputs an external control part signal necessary for the bus access, and the read data are stored in a read data register 12. These operations are repeated and a string processing deciding part 6 decides the end of an access based on the contents of the counter 5. Thus the end of the access given to the string data is attained with no use of a conditional branch microinstruction. As a result, the access time is shortened to the string data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device that performs a cycloprogram control operation.

[Conventional technology]

Conventional information processing devices such as microprocessors that have a pipeline configuration and perform microprogram control operations are
When accessing string data in main memory connected via a bus, if all of the string data cannot be completed in a single bus transfer due to bus width constraints, multiple bus transfers are performed to complete the process. A microprogram determines whether bus transfer has been executed a predetermined number of times.

An example of an operation using a conventional information processing device will be described with reference to FIGS. 4, 5, 6(A), and 6(B).

FIG. 4 shows the string data that is accessed, and the string data S is the first read data X,
It consists of second read data y and third read data 2. Here, the width of one access is 4 bytes. Figure 5 shows the string data S in the main memory of Figure 4.
2 is a flowchart showing the operation when accessing . FIGS. 6(A) and 6(B) show each stage of the pipeline of a conventional information processing device according to the operation shown in the flowchart of FIG.
The flow of processing in the address calculation execution stage, bus access stage, and operation execution stage is shown. Here, only reading of string data S will be explained.

First, time t. Then, the string data length “9” is written to the counter.
A microinstruction i for setting " is fetched from the control storage unit in a fetch cycle f1 of the fetch stage. Subsequently, at time t1, an instruction 2 is decoded in a decode cycle d1 of the Tefodo stage. Microinstruction 11 for reading string data
is retrieved from the control store in fetch cycle fII.

Next, at time t2, based on the coded result of instruction j, a total of 3 addresses! In the address calculation execution cycle a+ of the execution stage, the string data length ``9'' is set in the counter (step 5A in FIG. 5).At this time, instruction 11 is further decoded in the decode cycle d, and the string data is A branch microinstruction (■) for determining whether or not all has been read is taken out from the control storage unit in a fetch cycle f.Furthermore, at time t3, data is fetched in an address calculation execution cycle a based on the decoding result of the instruction 11. Address "101" is generated.

At this time, the instruction ■
is decoded and the microinstruction V is fetched from the control store in a fetch cycle f. Next, at time t, 4 bytes of string data are read in the bus access cycle Bu of the bus access stage (step 5B), and the reading is completed in the address calculation execution cycle a□ based on the result of the code in the instruction field. Decide whether or not.

In this case, 5 bytes of string data remain υ・
Therefore, it is determined to continue reading and branches to instruction iv (step 5C). Next, at time, the operation is executed in the operation execution cycle e1 of the operation execution stage, and the microinstruction 1■ to subtract the contents of the counter by ``4''4'' is fetched from the control storage unit in the fetch cycle f6. taken out.

That is, the fetch cycle fv of the microinstruction fetch stage is carried out, and the microinstruction j1
is retrieved from the control store in a fetch cycle f. Subsequently, at time t7, the contents of the counter are subtracted from "9" to "5" in address calculation execution cycle alV based on the decoding result of instruction iv (step 5D). At the same time, instruction 11 is decoded in the decode cycle (] II and the microinstruction city is decoded in the fetch cycle f
It is retrieved from the control storage at IIl. Instruction il, instruction street, instruction I until all string data has been read.
V is repeated, and when it is determined that reading is complete, the program advances to instruction V.

[Problem to be solved by the invention]

When reading string data, the conventional information processing device described above uses a microinstruction to determine whether or not all of the string data has been read. As a result, it is necessary to take out a new branch destination microinstruction, which has the disadvantage that the string data is not accessed and the time required increases.

An object of the present invention is to provide an information processing device that solves the above problems.

[Means to solve the problem]

The information processing device of the present invention includes a reading unit that reads a microinstruction from a control storage unit every time a predetermined time elapses, and a readout unit that reads the microinstruction that was read out by the reading unit the predetermined time ago. a decoder for decoding and generating a group of control signals; and a total data transfer amount specified based on at least a portion of the control signal group obtained as a result of decoding a string data transfer microinstruction, and a single bus data transfer. When the total data transfer amount is larger than the bus data transfer amount, the operations of the extracting means and the decoding means are stopped. transfer control means for outputting bus transfer instructions at predetermined time intervals as many times as necessary to transfer the amount of data to the bus; storage means for temporarily storing data; The storage device includes bus control means for transferring data via a bus between the storage device and the storage means in response to a transfer instruction.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

Referring to FIG. 1, a microprocessor 20 according to an embodiment of the present invention includes a microinstruction register, a microinstruction decoder 2, a pipeline register 3, a string access fluff section 4, a subtraction counter 5, and a string access fluff section 4. Process determination unit 6, address generation unit 77, 7F address register 8, flow program card 9, pipeline control unit 10, bus access control unit 11, read cheater register 2, write data register 3, general purpose register It is composed of a pointer section 14, a general-purpose register group 15 including a plurality of general-purpose registers, a bus access signal generation section 16, and registers 7, 18, and I9. A clock signal is supplied to each component, so that each component operates synchronously. The contents of registers 17, 18 and 19 are updated by the contents of pipeline register 3° registers 17 and 18 in synchronization with the twisted clock signal.

Next, the operation of this embodiment will be explained with reference to FIGS. 1 to 4.

FIG. 2 is a flowchart showing the operation when accessing the string data S stored in the main memory device of FIG. 4.

FIG. 3 shows each stage of the pipeline of microprocessor 20 according to the operation shown in the flowchart of FIG.
fetch stage.

Tecoat station, address calculation execution stage.

The flow of processing in the bus access stage and the arithmetic execution stage is shown. Here, only reading string data will be explained.

First, a microinstruction I for setting a string data length of ``9'' in the counter 5 is fetched from the control storage unit (not shown) in the fetch cycle fQ of the fetch stage, and is stored in the microinstruction register 1 at time t0. Then, the TECODE cycle d of the TECODE station.

The instruction I0 is decoded by the microinstruction decoder 2, and the decoding result is stored in the pipeline register 3 as a control command at time tl. At this time, at the same time, a microinstruction 11 for reading string data is fetched from the control storage section in a fetch cycle f, and is stored in the microinstruction register l at time t1. At the same time t1, the contents of the pipeline register 3 are further stored in the register 17. Next, at time t2,
After the contents of the pipeline register 3 are stored in the register 17, part of the control command in the register 17 is given to the counter 5 in the address calculation execution cycle aO of the address calculation execution stage, and as a result, the string data is stored in the counter 5. A long “9” is set (Step 2 in Figure 2).
A). At the same time, instruction 11 is decoded by microinstruction defuuter 2 in decode cycle d1, and at time t2,
The second decoding result is stored in the pipeline register 3 as a control command, and the next microinstruction is taken out from the control storage section in the fetch cycle f2 and stored in the microinstruction register 1 at time t2. Here, the command stored in pipeline register 3 is ON.
Contains a status string access flag section 4. continue,
At time t3, after the contents of pipeline register 3 are stored in register 17, address calculation execution cycle a1
Based on the control command stored in the register 17, the data address "101" is generated by the address generation section 7 and set in the 7 address register 8. At the same time, the next microinstruction is decoded by the microinstruction decoder 2 in the decode cycle d2, and at time t3, the next microinstruction is stored in the pipeline register 3 as a control command, and the next microinstruction is decoded in the fetch cycle f3. It is taken out from the control storage section and stored in the microinstruction register 1 at time t3. Here, since the content of the counter 5 is “9” and the string access flag unit 4 is in the ON state, the string processing determination unit 6 cannot read all of the string data with only this access. The pipeline control unit]0
instructs the fetch stage and leverage F stage to stop. That is, pipeline register 3. Updating of the contents of program counter 9 and microinstruction register 1 is stopped, and as a result, fetch cycle f and decode cycle d2 are postponed. However, the contents of the counter 5 are subtracted from "9" to "5" by 4", which corresponds to the 4 bytes read this time.

Furthermore, at time t4, the contents of register 17 are stored in register 18, and based on the contents of register 17, bus access is performed in bus access cycle B) of the bus access stage. That is, the bus access control unit 11
In accordance with instructions from the bus access signal generator 16, external control signals necessary for bus access are generated and output, and the read data is stored in the X-F data register 12. At the same time, the address is added by 4 bytes in address calculation execution cycles a and 2 to become "105", which is stored in the address register 8 at time t. Here, the string processing determination unit 6 determines that the content of the counter 5 is S′“ and the string access flag unit 4 is ON.
Since it is in this state, it is determined that string data access is necessary next time as well, and the pipeline control unit IO is instructed to continue stopping the operations of the fetch stage and the code stage. However, the content of counter 5 changes from °゛5'' to 1'', which corresponds to the 4 bytes read this time.
will be subtracted. Next, at time t5, the contents of register 18 are stored in register 19, and based on the contents of register 18, read data X is transferred to general-purpose register group 15 in operation execution cycle e1 of the operation execution stage, and the general-purpose register pointer The contents of section 14 are updated. At this time, at the same time, based on the contents of the register 18, a bus access is performed in the bus access cycle Bl', the read data y is stored in the read data register 12, and the address counter)E[row cycle a1 '', the address is added by 4 bytes and becomes ``109'', which is stored in the address register 8 at time t5. Here, the string processing determination unit 6 determines that the content of the counter 5 is 1" and the value of the lowest two hints of address "109" is "01", so the remaining string data does not exist across the next block address. Therefore, it determines that the access will be completed next time and instructs the pipeline control unit 10 to release the suspension of operations at the fetch stage and the Tefute' stage.In other words, the pipeline register 3, program counter 9, and microinstruction are The contents of register 1 are updated, and therefore the fetch cycle f and decode cycle d2 are completed, the normal pipeline processing operation returns, and the string access flag unit 4 becomes OFF.Subsequently, at time t, , based on the contents of register) 9, the ret data y is transferred to the general-purpose renostar group 15 in the operation execution cycle e, and the contents of the general-purpose register pointer section 14 are updated.At the same time, based on the contents of register]9, , bus access cycle B,'' bus access is performed, and the read data l is stored in the read data register 12. Furthermore, at time t7, the ret data Z is general-purposed in the operation execution cycle e1'' and the register group 1
5, and the contents of the general-purpose register pointer section 14 are updated. Therefore, data x containing string data S
, y, and t are completed (step 2B).

〔Effect of the invention〕

As explained above, the present invention has a feature that when accessing string data, the access can be completed without using a conditional branch microinstruction, so that the access time to the string data can be shortened. effective.

[Brief explanation of the drawing]

1 is a diagram showing an embodiment of the present invention, FIG. 2 is a flowchart showing the operation when accessing the string data S stored in the main memory device of FIG. 4, and FIG. 3 is a diagram showing an embodiment of the present invention. A diagram showing the flow of the pipeline processing of this embodiment according to the operation shown in the flowchart, FIG. 4 is a diagram showing string data to be accessed, and FIG. 5 is a diagram showing the string data stored in the main storage device of FIG. 4. FIG. 6(A) and FIG. 6(B) are diagrams showing the flow of pipeline processing in the conventional example according to the operation shown in the flowchart of FIG. 5. It is. 1...Microinstruction register, 2...
Microinstruction decoder, 3... Pipeline register, 4... String access flag section,
5... Subtraction counter, 6... String processing determination section, 7... Address generation section, 8...
...Address register, 9...Frogram counter, 10...Pipeline control L11...
... Bus access control L 12 ... Read data register, 13 ... Write data register, 1
4...General-purpose register pointer section, 15...
... General-purpose register group, 16 ... Bus access signal generation unit, 17 ... Register, 18 ... Register, 19 ... Register, 20 ... Microprocessor. Agent Patent Attorney Susumu Uchihara”21)-e;7 t:l '7'd Shizuku, Evening Flash

Claims (1)

[Scope of Claim] In an information processing device that is connected via a bus to a storage device for storing data and that performs microprogram control operations, the control memory stores the microprogram every predetermined time period. reading means for reading a microinstruction from a string data transfer microinstruction; decoding means for decoding the microinstruction read out by the reading means a predetermined time ago to generate a group of control signals; The total data transfer amount specified based on at least a part of the control signal group obtained as a result of decoding is compared with a predetermined bus data transfer amount that can be transferred by one bus data transfer, and the total data transfer amount is determined. If it is larger than the bus data transfer amount, the operation of the reading means and the decoding means is stopped, and the bus transfer instruction is issued as many times as necessary to transfer the data corresponding to the total data transfer amount over the predetermined time period. transfer control means for outputting the data at intervals of , storage means for temporarily storing the data, and communication between the storage device and the storage means via the bus in response to the bus transfer instruction; An information processing device comprising: bus control means for transferring data.