JPH04107745A - In-circuit emulator - Google Patents

Abstract

PURPOSE:To prevent the runaway of a program occurring by generating a CPU stopping instruction code, inputting an instruction non-selection signal generated with an instruction code request signal when the value of an address signal and an address comparison value is not equal, and reading it in a CPU. CONSTITUTION:An address monitoring circuit 4 generates an instruction code address signal 5 and a memory selection signal 6 when memory is allocated to an address by the address signal 2 and the instruction code request signal 3, and generates a memory non-selection signal 9 when no memory is allocated to the address. A memory circuit 7 outputs the instruction code of a corresponding address to a data bus 8 when the instruction code signal 5 and the memory selection signal 6 are inputted, and reads it in the CPU 1. A buffer 10 for CPU stopping instruction code generation generates the instruction code to stop the CPU 1 from the memory non-selection signal 9, and outputs it to the data bus 8, and reads it in the CPU 1. In such a way, it is possible to prevent the runaway of the program occurring when an instruction is executed in an area where no memory is allocated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an in-circuit emulator, and particularly to an in-circuit emulator having a mechanism to prevent runaway due to program errors during program debugging.

[Conventional technology]

In general, in-circuit emulators are used when developing products that use a CPU.
It is connected as a substitute for the PU and is used to debug hardware and programs.In particular, the address monitoring circuit allows free allocation in the memory space so that programs can be developed even when the hardware is not completed. It has a built-in memory circuit that can be changed.

A block diagram of a configuration example of a conventional in-circuit emulator is shown in FIG.

The in-circuit emulator is composed of a CPUI, an address monitoring circuit 4, and a memory circuit 7, each of which has an address signal 2, an instruction code request signal 3, an instruction code address signal 5, a memory selection signal 6, and a data bus 8.
electrically connected.

In order to execute a program, the CPU outputs an address signal 2 and an instruction code request signal 3, and reads the instruction code from the memory circuit 7 via the data bus 8.

At this time, the address monitoring circuit 4 converts the address signal 2 and instruction code request signal 3 outputted from the CPUI into an instruction code address signal 5 and a memory selection signal 6 according to a preset conversion procedure, and sends them to the memory circuit 7. Output.

This realizes the memory circuit 7 that can freely change the allocation in the memory space.

Problems to be Solved by Invention In the conventional in-search/emulation system, if a program error causes an instruction code to be read from an address that is not allocated to the aforementioned memory circuit, a meaningless instruction code is read, As a result, in the worst case, the program would run out of control.The purpose of the present invention is to The purpose is to provide an in-search software emulator that will not run out of control.

[Means to solve the problem]

The in-circuit emulator of the present invention includes a CPU;
an address monitoring circuit that inputs an address signal and an instruction code request signal output from the CPU and generates an instruction code address signal and a memory selection signal; and an address monitoring circuit that inputs the instruction code address signal and the memory selection signal and generates an instruction code. an in-circuit emulator having a memory circuit that supplies a signal to the CPU via a datum, wherein the address monitoring circuit or an address comparison circuit having a predetermined address comparison value is provided, and the value of the address signal or the address comparison value is If the instruction code request signal does not match, a memory non-selection signal is generated together with the instruction code request signal.
Create a U suspension command code and read it into the CPU.
It is configured by adding a U-stop command code generation circuit.

Further, the in-circuit emulator of the present invention includes the CPU stop instruction code generation circuit, buffer, or memory circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a diagram of one embodiment of the present invention.

The in-circuit emulator is composed of a CPUI, an address monitoring circuit 4, a memory circuit 7, and a CPLI stop instruction code buffer 10, each of which has an address signal 2, an instruction code request signal 3, an instruction code address signal 5, and a memory circuit. CP (Jl) inputs and outputs the selection signal 6, data bus 8, and memory non-selection signal 9.
is output, and the instruction code is read from the data bus 8 and executed.

The address monitoring circuit 4 generates an instruction code address signal 5 and a memory selection signal 6 from the address signal 2 and the instruction code request signal 3 in the case of an address to which memory is allocated, and in the case of an address to which no memory is allocated,
A memory non-selection signal 9 is generated.

The memory circuit 7 receives an instruction code signal 5 and a memory selection signal 6.
When an instruction code of the corresponding address is input, the instruction code of the corresponding address is output to the data bus 8 and read by the CPU.

The CPU stop instruction code generation buffer 10 generates an instruction code for stopping the CPU 1 from the memory non-selection signal 9, outputs it to the data bus 8, and causes the CPU 1 to read it.

The CPU 1 outputs an address signal 2 and an instruction code request signal 3 to the address monitoring circuit 4 in order to execute the program.

In the case of an address to which memory is allocated, the address monitoring circuit 4 outputs an instruction code address signal 5 and a memory selection signal 6 to the memory circuit 7, and the instruction code is read into the CPUI through the data bus 8.

The CPU 1 executes the read instruction code.

In the case of an address to which no memory has been allocated, the address monitoring circuit 4 outputs a memory non-selection signal 9 to the CPLI stop instruction code generation buffer 10.

When the memory non-selection signal 9 is input to the CPU stop command code generation buffer 10, the CPU stop command code is read into the CPU 1 from the CPU stop command code generation buffer through the data bus.

When the read instruction code is executed, the CPU immediately stops operating because it is a CPU stop instruction code.

Next, in the in-search soto emulator, which will be explained in more detail, the address monitoring circuit 4 has an address conversion circuit 1 and an address comparison circuit 2, each of which receives an address signal 2, a memory memory It inputs a read request signal 3 and outputs an instruction code address signal, an address match signal 13, and an address mismatch signal 14.

The CPUI sends an address signal 2 and a memory read request signal 3.
is output, and the instruction code is read from the data bus 8 and executed.

When the address signal 2 is input, the address conversion circuit 11 converts the address signal 2 into an instruction code address signal 5 according to a preset conversion value.

When address signal 2 is input, address comparison circuit 12 outputs either address match signal 13 or address mismatch signal 14 according to a preset comparison value.

The CPU stop command code generation buffer 10 corresponds to the CPU stop command code generation circuit 10 in FIG. Load it.

The memory selection signal 6 is a signal obtained by ANDing the address match signal 13 and the memory read request signal 3, and is input to the memory circuit 7.

The memory non-selection signal 9 is a signal obtained by ANDing the address mismatch signal 14 and the memory reread request signal 3.
The CPU stop instruction code is input to the buffer 10 for generating the instruction code.

In order to execute a program, the CPUI outputs an address signal 2 to an address conversion circuit 11 and an address comparison circuit 12, and simultaneously outputs a memory read request signal 3.

When the value of the address signal 2 output by the CPU 1 matches the address allocated to the memory, the address conversion circuit 11 converts the address signal 2 and outputs the instruction code address signal 5, and the address comparison circuit 12 An address match signal 13 is output.

This address match signal 13 is the memory REET request signal 3.
After performing an AND operation with the instruction code address signal 5 to obtain the memory selection signal 6, the signal is input to the memory circuit 7 together with the instruction code address signal 5.

As a result, the corresponding instruction code is output from the memory circuit 7 and read into the CPU 1 via the data bus 8. The CPUI executes the read instructions.

Further, if the value of the address signal 2 outputted by the CPUI does not match the address allocated to the memory, the address comparison circuit 12 outputs an address mismatch signal 14.

This address mismatch signal 14 is logically ANDed with the memory read request signal 3 to become a memory non-selection signal, and then inputted to the CPU stop instruction code generation buffer 10.

As a result, the CPU stop instruction code generation buffer 10
A CPU stop instruction code is output from the CPU 1 and read into the CPU 1 via the data bus 8.

In this embodiment, the CPU stops immediately when the read instruction code is executed. Similar results can be obtained using a more sophisticated memory circuit.

〔Effect of the invention〕

As explained above, the in-circuit emulator of the present invention has the effect of preventing a program from running out of control when an instruction is executed in an unallocated area of memory.

No., 10... CP and stop instruction code generation ha... lfa, 11... address conversion circuit, 12... address comparison circuit, 13... address match signal, 14. address mismatch. signal.

Claims (1)

[Claims] 1. A CPU, an address monitoring circuit that receives an address signal and an instruction code request signal output from the CPU and generates an instruction code address signal and a memory selection signal, and the instruction code address signal. and the memory selection signal, and the instruction code is sent to the CP via the data bus.
In the in-circuit emulator, the address monitoring circuit includes an address comparison circuit having a predetermined address comparison value, and when the value of the address signal does not match the address comparison value, the address monitoring circuit An in-circuit emulator further comprising a CPU stop instruction code generating circuit which inputs a memory non-selection signal generated together with a code request signal, generates a CPU stop instruction code, and causes the CPU to read the generated CPU stop instruction code. 2. The in-circuit emulator according to claim 1, wherein the CPU stop instruction code generation circuit has a buffer or a memory circuit.