JPH04111432A - Field-effect transistor and its manufacture - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to field effect transistors, particularly electric field transistors that can realize high frequency operation used in microwave integrated circuits (MICs) and monolithic microwave integrated circuits (MMICs). This invention relates to an effect transistor and its manufacturing method.

[Conventional technology]

GaAsMMI for high frequency operation in the microwave band
C and MIC are constructed by combining an active element such as a field effect transistor and a light receiving element such as a resistor, capacitor, and inductance. Here, since the operating frequency of the field effect transistor used is extremely high, 2 GHz or more, the transistor itself is required to have high speed. Therefore, it is necessary to improve the current cutoff frequency f1, which indicates high speed. Specific methods for improving fl include a method of improving transconductance g and reducing the amount of gate 8, and a method of making the ohmic region low in resistance.

Therefore, in the conventional manufacturing method of field effect transistors,
0.5 μm to improve g ゛ and reduce gate capacitance
The following short gates were installed. Furthermore, in order to reduce the source resistance, a method has been considered in which ions are implanted into the ohmic region in self-alignment with the gate electrode and activated to provide a low resistance region.

[Problem to be solved by the invention]

However, if the ohmic region is made to have a low resistance by ion implantation symmetrically with the gate electrode in a self-aligned manner, the drain-gate breakdown voltage becomes low and current-voltage saturation characteristics deteriorate. Furthermore, the drain conductance also deteriorates for the same reason.

Therefore, an object of the present invention is to provide a field effect transistor with high fT.

Another object of the present invention is to provide a manufacturing method that can easily form a short gate and manufacture a field effect transistor with high f.

[Means to solve the problem]

In order to achieve the above object, a field effect transistor according to the present invention includes a low resistance region formed only in a source formation portion of a semiconductor substrate, a source electrode formed on this low resistance region, and a gate formation portion of the semiconductor substrate. a dummy gate formed on the drain formation part; a gate electrode installed so as to be in contact with a part of the side surface and top surface of the dummy gate located on the drain formation part side of the semiconductor substrate; and a gate electrode formed on the drain formation part. and a drain electrode.

Further, the method for manufacturing a field effect transistor according to the present invention includes a step of forming a mask pattern having an opening on a source formation portion of a semiconductor substrate, a step of forming a dummy gate on the gate formation portion of the opening, and a step of forming a dummy gate on the gate formation portion of the opening. A step of injecting impurities into the semiconductor substrate in a self-aligned manner using the gate and the mask pattern to make the source formation part low in resistance, and removing the mask pattern and implanting the impurity in the semiconductor substrate located on the side of the drain formation part. The method includes a step of forming a gate electrode so as to be in contact with a portion of a side surface and a top surface of the dummy gate.

[Effect]

In the field effect transistor according to the present invention, only the resistance between the source and the gate is reduced, but the breakdown voltage between the gate and the drain is not reduced. Therefore, the field effect transistor has a high fT and a high breakdown voltage.

In addition, according to the manufacturing method of the present invention, impurities are implanted in a self-aligned manner using a dummy gate, so the source formation part is placed with high precision, and the gate is formed overlapping the dummy gate, so the gate length can be reduced at least. The aperture width can be made smaller than the aperture width obtained by optical exposure.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS A field effect transistor and a method for manufacturing the same according to an embodiment of the present invention will be described below with reference to the accompanying drawings. In the description, the same elements are denoted by the same reference numerals, and redundant description will be omitted.

FIG. 1 is a longitudinal sectional view showing the structure of a field effect transistor according to one embodiment. An active layer 1 is formed on the upper surface of the semiconductor substrate 1.
A is formed, and its source/forming portion 1s has become a low resistance region IS by ion implantation of impurities or the like. A source electrode S is formed in ohmic contact on this low resistance region 1s. In addition, a dummy gate G is formed in the gate formation portion of the semiconductor substrate 1 via a SiN film 2, so that it partially overlaps with the dummy gate G.
A gate electrode G is formed. This gate electrode G is formed on the side opposite to the source formation part, that is, on the drain formation part side. Further, a drain electrode is formed on the drain formation portion with the SfN film 2 interposed therebetween.

In this way, according to the field effect transistor of this embodiment, after the dummy gate Gd is formed, the gate electrode is placed overlappingly on the side where the drain is formed, so that the gate length of the gate electrode can be shortened. can do. In addition, since only the source forming part has low resistance, g 1 fr
and improved drain conductance. Note that since the gate electrode is placed on the insulating film only on the source side, Cg (gate-drain capacitance) does not increase.

FIG. 2 is a process diagram showing a method for manufacturing a field effect transistor using a GaAs substrate. First, semi-insulating GaAs
Si ions are implanted onto the substrate 1, and then the ion implanted portion is activated by annealing to form an active layer 1a on the substrate surface. A SiN film 2 is deposited on top of this active layer 1a by plasma CVD (FIG. 2(a)). Note that the active layer 1a may be formed by an epitaxial growth method.

Next, a resist pattern 3 having an opening in the source formation region of the GaAs substrate 1 is formed on the SiN film 2 (FIG. 3(b)). The SiN film 2 is exposed in this opening.

Further, an S 102 film 4 having a thickness of, for example, 5000 to 6000 angstroms is deposited on the upper surface of this resist pattern 3 by sputtering (FIG. 3(C)). Thereafter, by etching back the SiO2 film 4 using RIE, the S l attached to the source formation region side of the resist pattern 3 is removed.
02 film 4 constitutes a dummy gate Gd (
Figure (d)). Although the SiO2 film is deposited here, a SiN film may be deposited by, for example, the ECR-CVD method.

Next, using the resist pattern 3 and the dummy gate Gd, Si ions are deeply implanted into the GaAs substrate 1 to form a low resistance region IS only in the source formation region. after that,
Remove the resist pattern 3 and expose the SiN film 2 (
Figure (e)). The Si ions in this implanted region are activated by annealing.

Next, an opening is formed in the SiN film 2 located on both sides of the dummy gate Gd, and a source electrode S and a drain electrode are formed on the active layer 1a by ohmic contact (FIG. 3(f)).
, a resist pattern 5 for forming a gate is formed. At this time, even if the opening width of the resist pattern 5 is 0.6 μm, a sufficient opening can be made by optical exposure such as photolithography technology. Thereafter, the SiN film 2 is removed using RIE based on this resist pattern 5 (
Figure (g)).

Next, a multilayer metal film 6 made of Ti/Pt/Au is deposited using a vapor deposition method, for example, with a thickness of 500/30015000.
The resist pattern 5 is deposited with a film thickness of angstroms on the upper surface of the resist pattern 5 and its opening ((h) in the same figure), and finally, the resist pattern 5 is removed by lift-off to form a field effect transistor ((i) in the same figure). . For example, even if the dummy gate Gd is formed with the maximum opening width of 0.6 μm by optical exposure, the gate G will be formed overlapping the dummy gate Gd, so that the substantial (active layer 1a
(contact with) can reduce the gate length. The width of the dummy gate G can be adjusted by changing the thickness of the S t O2 film 4 (see figure (c)), and the actual gate length of the gate G can be adjusted by changing the width of the dummy gate Gd exposed from the resist pattern 5. This can be easily changed by changing the degree of (see (h) in the same figure).

In this way, by adjusting the thickness of the SiO2 film 4 and the extent of the dummy gate Gd exposed from the resist pattern 5, a gate having a gate length on the order of submicrons can be easily formed.

Further, since the distance between the gate and the low resistance region 1s can be determined in a self-aligned manner depending on the length of the dummy gate G, the distance between the gate G and the low resistance region 1s can be accurately arranged.

Furthermore, since the impurity is deeply implanted only in the region below the source electrode S in a self-aligned manner with the dummy gate, the source resistance can be reduced without lowering the breakdown voltage between the gate and drain.

Note that the present invention is not limited to the above embodiments.

Although the field effect transistor according to the above embodiment uses a GaAs substrate, it goes without saying that the substrate is not limited to GaAs.

〔Effect of the invention〕

The field effect transistor according to the present invention has a structure in which a low resistance region is formed only in the region below the source electrode, and the gate electrode is overlapped with the dummy gate.
High frequency characteristics can be improved without lowering the breakdown voltage between the drains.

Further, the manufacturing method according to the present invention allows field effect transistors with high high frequency characteristics to be manufactured with high precision.

film.

Claims (1)

[Claims] 1. A low resistance region formed only in a source formation portion of a semiconductor substrate, a source electrode formed on the low resistance region,
a dummy gate formed on the gate formation part of the semiconductor substrate; a gate electrode installed so as to be in contact with a part of the side surface and top surface of the dummy gate located on the drain formation part side of the semiconductor substrate; A field effect transistor comprising a drain electrode formed on a drain forming part. 2. forming a mask pattern having an opening over the source formation portion of the semiconductor substrate; forming a dummy gate over the gate formation portion of the opening; using the dummy gate and the mask pattern;
Injecting impurities into the semiconductor substrate in a self-aligned manner to make the source formation part low in resistance; and removing the mask pattern and implanting a part of the side surface and top surface of the dummy gate located on the drain formation part side. forming a gate electrode in contact with the field effect transistor.