JPH04111460A - Hybrid integrated circuit device - Google Patents

Hybrid integrated circuit device

Info

Publication number
JPH04111460A
JPH04111460A JP2228265A JP22826590A JPH04111460A JP H04111460 A JPH04111460 A JP H04111460A JP 2228265 A JP2228265 A JP 2228265A JP 22826590 A JP22826590 A JP 22826590A JP H04111460 A JPH04111460 A JP H04111460A
Authority
JP
Japan
Prior art keywords
integrated circuit
board
sub
circuit device
hybrid integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2228265A
Other languages
Japanese (ja)
Other versions
JP2828753B2 (en
Inventor
Kikuo Isoyama
磯山 貴久雄
Yuusuke Igarashi
優助 五十嵐
Kazunori Takashima
和典 高島
Yoshiyuki Kobayashi
義幸 小林
Sumio Ishihara
石原 純夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP2228265A priority Critical patent/JP2828753B2/en
Publication of JPH04111460A publication Critical patent/JPH04111460A/en
Application granted granted Critical
Publication of JP2828753B2 publication Critical patent/JP2828753B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/14Structural association of two or more printed circuits
    • H05K1/141One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/14Structural association of two or more printed circuits
    • H05K1/144Stacked arrangements of planar printed circuit boards
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/541Dispositions of bond wires
    • H10W72/5445Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Combinations Of Printed Boards (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 (イ)産業上の利用分野 本発明は多層金属基板構造の混成集積回路装置に関する
DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a hybrid integrated circuit device having a multilayer metal substrate structure.

(ロ)従来の技術 第4図を参照して従来の多層金属基板構造の混成集積回
路装置を説明する。
(b) Prior Art A conventional hybrid integrated circuit device having a multilayer metal substrate structure will be described with reference to FIG.

同図は混成集積回路装置の断面構造を示し、混成集積回
路装置は2枚の絶縁金属基板(62)(64)、接着性
の絶縁樹脂層(66)、導電路(68)、パッド(70
)、集積回路素子(72)、チップ抵抗あるいはチップ
コンデンサ等のチップ素子(74)、ケース材(75)
、対の内部リード(76)等で示されている。
The figure shows a cross-sectional structure of a hybrid integrated circuit device, which consists of two insulating metal substrates (62) (64), an adhesive insulating resin layer (66), a conductive path (68), and a pad (70).
), integrated circuit elements (72), chip elements such as chip resistors or chip capacitors (74), case materials (75)
, a pair of internal leads (76), etc.

絶縁金属基板(62)(64)には陽極酸化処理したア
ルミニウム基板が主として使用され、絶縁樹脂層(66
)を介して貼着しだ銅箔をホトエツチングする等して導
電路(68)およびパッド(70)が所定のパターンに
形成される。
Anodized aluminum substrates are mainly used for the insulating metal substrates (62) and (64), and the insulating resin layer (66
), conductive paths (68) and pads (70) are formed in a predetermined pattern, such as by photo-etching the copper foil pasted through the copper foil.

集積回路素子(72)は導電路(68)の所定の位置に
Agペースト等を使用して固着され、その他のチップ素
子(74)および外部リード(参照番号を付さない)は
所定の導電路(68)に半田固着される。
The integrated circuit element (72) is fixed in a predetermined position on the conductive path (68) using Ag paste or the like, and the other chip elements (74) and external leads (no reference numbers) are attached to the predetermined conductive path (68). (68) is fixed by solder.

また、略り字形状の内部リード(76)は、搭載素子が
対向するように2枚の絶縁金属基板(62)(64)を
ケース材(75)に固着したときに、それぞれの絶縁金
属基板(62)(64)のパッド(70)に固着された
内部リード(76)の他端が当接するようにパッド(7
0)に半田固着される。内部リード(76)のこの当接
部はリフローにより半田固着され、2枚の絶縁金属基板
(62)(64)上に形成された導電路(68)が相互
接続される。
Furthermore, when the two insulated metal substrates (62) and (64) are fixed to the case material (75) so that the mounted elements face each other, the abbreviated internal leads (76) Pad (7) so that the other end of internal lead (76) fixed to pad (70) of (62) and (64) comes into
0) is fixed by solder. This contact portion of the internal lead (76) is soldered and fixed by reflow, and the conductive paths (68) formed on the two insulated metal substrates (62) (64) are interconnected.

上記構造によれば、混成集積回路装置の投影面積を低減
することができる他、2枚の絶縁金属基板(62)(6
4)の何れにも大電力の集積回路素子を搭載することが
できる。
According to the above structure, in addition to being able to reduce the projected area of the hybrid integrated circuit device, the two insulated metal substrates (62) (6
4) A high-power integrated circuit element can be mounted on any of the above.

(ハ)発明が解決しようとする課題 しかしながら、上記構造の混成集積回路装置においては
、導電路の相互接続が可能な個所が絶縁金属基板端部に
限定されるため、所定の導電路を絶縁金属基板端部に導
かねばならない問題を有する。特にマイクロコンピュー
タを搭載する昨今の混成集積回路装置では相互接続を必
要とする導電路の数が膨大であるため、この導電路の引
き回しによって多大な素子実装面積が消費される欠点を
有している。
(c) Problems to be Solved by the Invention However, in the hybrid integrated circuit device having the above structure, the locations where conductive paths can be interconnected are limited to the ends of the insulated metal substrate. This has the problem of having to be guided to the edge of the substrate. In particular, modern hybrid integrated circuit devices equipped with microcomputers have a huge number of conductive paths that need to be interconnected, and the disadvantage is that a large amount of device mounting area is consumed by routing these conductive paths. .

また、16ビツト以上のマイクロコンピュータを搭載す
る場合には、そのデータバス、アドレスバスの幅は一回
のワイアボンディングによっては横断が不可能な大きさ
となるため、これらバスを横断する導電路の接続はこれ
までジャンピングワイア接続と称される技術により数時
に分けて行われている。このため、ジャンピングワイア
接続のための多数のパッドにより多大な素子実装面積が
消費される欠点も有している。
In addition, when a microcomputer with 16 bits or more is installed, the width of the data bus and address bus becomes so large that it is impossible to cross them with a single wire bonding, so it is necessary to connect conductive paths that cross these buses. Until now, this has been done in several parts using a technique called jumping wire connection. Therefore, it also has the disadvantage that a large number of pads for connecting jumping wires consumes a large amount of device mounting area.

さらには、上記混成集積回路装置はそれぞれの絶縁金属
基板をケース材に固着した後に内部リードの半田固着が
行われるため、製造工程が煩雑であると共にその後の機
能試験が困難になるばかりか、トラブルシューティング
が不可能となる欠点を有している。
Furthermore, in the above-mentioned hybrid integrated circuit device, the internal leads are soldered after each insulated metal substrate is fixed to the case material, which not only complicates the manufacturing process but also makes subsequent functional tests difficult. It has the disadvantage that shooting is impossible.

に)課題を解決するための手段 本発明は上記課題に鑑みてなされたものであって、絶縁
金属基板上に所定形状に導電路を形成したサブ基板を、
マザー基板上に固着搭載した所定の集積回路素子に隣接
する位置であって、マザ基板上に所定間隔離間して固着
することによって高密度かつ高集積度の混成集積回路装
置を提供するものである。
B) Means for Solving the Problems The present invention has been made in view of the above problems, and includes a sub-substrate in which conductive paths are formed in a predetermined shape on an insulated metal substrate.
The device is located adjacent to a predetermined integrated circuit element fixedly mounted on the motherboard, and is fixed to the motherboard at a predetermined distance, thereby providing a high-density and high-integration hybrid integrated circuit device. .

(ホ)作用 所定形状に導電路を形成したサブ基板をマザー基板の所
定位置に配置するため、サブ基板の任意の周端部にてサ
ブ基板とマザー基板の導電路の相互接続を行うことが可
能となり、マザー基板の導電路の引き回しが抑制される
(e) Operation Since the sub-board with conductive paths formed in a predetermined shape is placed at a predetermined position on the mother board, the conductive paths of the sub-board and the mother board can be interconnected at any peripheral edge of the sub-board. This makes it possible to suppress the routing of conductive paths on the motherboard.

また、サブ基板の導電路によるマザー基板の導電路の長
スパンの接続が可能になってマザー基板の導電路の引き
回しが抑制されると共にジtンビング接続のためのパッ
ドが不要となる。
Further, it becomes possible to connect a long span of the conductive path of the mother board by the conductive path of the sub-board, thereby suppressing the routing of the conductive path of the mother board and eliminating the need for pads for digital connection.

さらに、サブ基板をマザー基板上に固着搭載した所定の
集積回路素子に隣接配置するため、所定の集積回路素子
の電極をマザー基板、サブ基板に形成したパッドの何れ
にも直接ワイアポンディングすることが可能になる。
Furthermore, in order to arrange the sub-board adjacent to a predetermined integrated circuit element fixedly mounted on the mother board, the electrodes of the predetermined integrated circuit element are directly wire-bonded to both the mother board and the pads formed on the sub-board. becomes possible.

さらにまた、サブ基板とマザー基板の主面が同一方向に
面するため、サブ基板とマザー基板の導電路の相互接続
後の機能試験、トラブルシュティングが容易になる。
Furthermore, since the main surfaces of the sub-board and the mother board face in the same direction, functional tests and troubleshooting after the interconnection of the conductive paths between the sub-board and the mother board are facilitated.

(へ)実施例 第1図乃至第3図を参照して本発明の一実施例を説明す
る。なお、第1図は実施例の平面図であり、第2図は第
1図の1−1線断面図である。また、第3図はサブ基板
の平面図である。
(f) Embodiment An embodiment of the present invention will be described with reference to FIGS. 1 to 3. Note that FIG. 1 is a plan view of the embodiment, and FIG. 2 is a sectional view taken along line 1-1 in FIG. Moreover, FIG. 3 is a plan view of the sub-board.

第1図および第2図に示されるように、本発明の混成集
積回路装置はマザー基板(10)上の所定位置にサブ基
板(30)を離間配置する基板構造を有する。
As shown in FIGS. 1 and 2, the hybrid integrated circuit device of the present invention has a substrate structure in which sub-boards (30) are spaced apart from each other at predetermined positions on a mother board (10).

マザー基板(10)には表面を陽極酸化処理した15〜
2.0mm厚のアルミニウム基板が使用され、接着性の
絶縁樹脂層(図示しない)により貼着しだ銅箔をホトエ
ツチングする等して例えばアドレスバス、データバス、
制御バス等の導電路(12)、集積回路素子(22)の
電極とワイアボンディングするためのパッド(14)、
外部リード用パッド(16)、マザー基板(10)とサ
ブ基板(30)上にそれぞれ形成した導電路とを相互接
続するためのバンド(18)およびサブ基板(30)の
支持部材を固着するためのパッド(20)等がその全面
に所定の)<ターンに形成される。
The motherboard (10) has a surface anodized to 15~
An aluminum substrate with a thickness of 2.0 mm is used, and an adhesive insulating resin layer (not shown) is attached, and a copper foil is photoetched to form, for example, an address bus, a data bus, etc.
A conductive path (12) such as a control bus, a pad (14) for wire bonding with an electrode of an integrated circuit element (22),
For fixing the external lead pad (16), the band (18) for interconnecting the conductive paths formed on the motherboard (10) and the sub-board (30), and the supporting member of the sub-board (30). Pads (20) and the like are formed on the entire surface in a predetermined turn.

マイクロコンピュータ、プログラマブル ゲートアレイ
、メモリ等の集積回路素子(22) (24) (26
)は所定のダイボンドパッド上にAgペースト等を使用
して固着され、特に発熱が多いパワー集積回路素子(2
2)(24)はヒートシンク(28)を介して固着され
る。また、チップ抵抗あるいはチップコンデンサ等のチ
ップ素子(図示されていない)は半田固着される。なお
、サブ基板(30)の直下に配置される集積回路素子(
26)の電極のワイアボンディングはサブ基板(30)
の固着前に行われる。
Integrated circuit elements such as microcomputers, programmable gate arrays, and memories (22) (24) (26
) is fixed on a predetermined die bond pad using Ag paste, etc., and is used for power integrated circuit elements (2) that generate a particularly large amount of heat.
2) (24) is fixed via a heat sink (28). Further, chip elements (not shown) such as chip resistors or chip capacitors are fixed by solder. Note that the integrated circuit element (
Wire bonding of the electrode in 26) is done on the sub-board (30)
This is done before the fixation of.

次に、第3図を参照してサブ基板(30)を説明する。Next, the sub-board (30) will be explained with reference to FIG.

同図は回路パターン形成および素子固着が完了したサブ
基板(30)の平面構造を説明する図であり、サブ基板
(30)はプレス成形により形成した孔(32)および
タブ(34)、接着性の絶縁樹脂層により片面、あるい
は両面に貼着しだ銅箔をホトエツチングする等して形成
した導電路(36)、パッド(38)(40)(42)
および所定のダイボンドパッド上にAgペースト等を使
用して固着した集積回路素子(46)等で示されている
This figure is a diagram explaining the planar structure of the sub-board (30) on which circuit pattern formation and element fixation have been completed. Conductive paths (36) and pads (38) (40) (42) formed by photo-etching copper foil adhered to one or both sides with an insulating resin layer.
and an integrated circuit element (46) fixed on a predetermined die bond pad using Ag paste or the like.

サブ基板(30)にはマザー基板(10)への半田固着
と強度を考慮して、錫、クロム、ニッケル、鉄等を含有
する略0.5mm厚の銅合金が使用される。
For the sub-board (30), a copper alloy with a thickness of approximately 0.5 mm containing tin, chromium, nickel, iron, etc. is used in consideration of solder adhesion to the mother board (10) and strength.

サブ基板(30)の導電路(36)はサブ基板(30)
上の回路素子を相互接続し、パッド(42)(18)を
介してマザー基板(10)上に形成した導電路(12)
と相互接続し、さらにはパッド(42)(18)を介し
て単にマザー基板(10)上に形成した導電路(12)
をジャンプ接続する。
The conductive path (36) of the sub-board (30) is connected to the sub-board (30)
Conductive paths (12) interconnecting the circuit elements above and formed on the motherboard (10) via pads (42) (18)
conductive paths (12) interconnected with and simply formed on the motherboard (10) via pads (42) (18);
Jump to connect.

タブ(34)は所定の工程において、その端部から略3
mmの位置でサブ基板(30)の面に直角に折り曲げら
れて、サブ基板(30)とマザー基板(10)の配置間
隔を略3mmに規制する支持部(34)となる。
In a given process, the tab (34) is approximately 3
The supporting portion (34) is bent perpendicularly to the surface of the sub-board (30) at a position of mm, thereby regulating the arrangement interval between the sub-board (30) and the mother board (10) to approximately 3 mm.

なお、この支持部(34)はサブ基板(30)の金属の
絞り加工によって形成することも、個別の支持部材によ
っても形成することも、さらには単にサブ基板(30)
の端部を折り曲げて形成することも可能である。また、
第3図は多面構成のサブ基板(30)を示しているが単
面構成であっても差し支えない。
Note that this support portion (34) may be formed by drawing the metal of the sub-board (30), or may be formed by an individual support member, or even simply by forming the support portion (34) on the sub-board (30).
It is also possible to form it by bending the end portion of it. Also,
Although FIG. 3 shows the sub-board (30) having a multi-sided configuration, it may also have a single-sided configuration.

再び第1図および第2図を参照して実施例をさらに詳細
に説明する。
The embodiment will be described in further detail with reference to FIGS. 1 and 2 again.

マザー基板(10)に形成したバンド(20)にサブ基
板(30)の支持部(34)を半田固着すると、第1図
に図示するように、サブ基板(30)の電子回路の構成
要素であって、放熱特性を考慮してマザー基板(10)
に固着された所定の集積回路素子(24)が、サブ基板
(30)に形成した孔(32)から露比すると共に集積
回路素子(24)にパフ)’ (40)が隣接配置され
る。従って、積層基板構造であるにもかかわらずサブ基
板(30)に高発熱の電子回路を形成することが可能と
なり、サブ基板(30)に分離形成される電子回路が制
限されない。
When the support part (34) of the sub-board (30) is soldered and fixed to the band (20) formed on the mother board (10), the electronic circuit components of the sub-board (30) are bonded to each other, as shown in FIG. Therefore, considering the heat dissipation characteristics, the mother board (10)
A predetermined integrated circuit element (24) fixed to the sub-board (30) is exposed through the hole (32) formed in the sub-substrate (30), and a puff (40) is placed adjacent to the integrated circuit element (24). Therefore, despite the laminated substrate structure, it is possible to form a highly heat generating electronic circuit on the sub-substrate (30), and the electronic circuit that can be formed separately on the sub-substrate (30) is not limited.

また、集積回路素子(22)にはマザー基板(10)の
パッド(工4)とサブ基板(30)のパッド(44)が
隣接配置される。このようなパッド配列は、例えばアド
レス信号がマザー基板(10)から供給され、その出力
データをサブ基板(30)に供給するようなROMに好
適であって、集積回路素子(22)の電極からマザー基
板(10)、あるいはサブ基板(30)のパッド(14
)(44)に直接ワイアボンディングできる本発明はワ
イアボンディング工程の削減効果並びに導電路面積の低
減効果が顕著である。
Furthermore, the integrated circuit element (22) has a pad (4) of the mother board (10) and a pad (44) of the sub-board (30) arranged adjacent to each other. Such a pad arrangement is suitable for, for example, a ROM in which an address signal is supplied from the mother board (10) and its output data is supplied to the sub-board (30), and the address signal is supplied from the electrode of the integrated circuit element (22). The pad (14) of the mother board (10) or sub board (30)
) (44) The present invention, which allows direct wire bonding to wire bonding, has a remarkable effect of reducing the wire bonding process and the area of the conductive path.

これら所定の集積回路素子(22)(24)はその電極
面がサブ基板(30)面と略等しい高さとなるように、
即ち所定の集積回路素子(22)(24)の電極とサブ
基板(30)のパラt’ (40)(44)が同一平面
に配列されるようにヒートシンク(28)を介して固着
される。そこで、少なくとも前記の集積回路素子(22
)(24)の電極とサブ基板(30)のパッド(40)
(44)間のワイアボンディングにおいては、ホンディ
ングヘッドを垂直方向に大きく移動させる必要がなくな
って、多ビンの集積回路が使用される混成集積回路装置
では特にワイアボンディング能率が向上する。
These predetermined integrated circuit elements (22) and (24) are arranged so that their electrode surfaces are approximately at the same height as the sub-substrate (30) surface.
That is, the electrodes of the predetermined integrated circuit elements (22, 24) and the para-t' (40, 44) of the sub-substrate (30) are fixed via the heat sink (28) so that they are arranged on the same plane. Therefore, at least the above-mentioned integrated circuit element (22
) (24) and the pad (40) of the sub-board (30)
In wire bonding between (44), there is no need to move the bonding head significantly in the vertical direction, and the wire bonding efficiency is improved, especially in a hybrid integrated circuit device in which multi-bin integrated circuits are used.

さらに、サブ基板(30)に形成したパッド(42)と
マザー基板(10)に形成したパッド(18)とをワイ
アボンディングすることにより、サブ基板(30)の電
子回路とマザー基板(10)の電子回路の相互接続が行
われ、またマザー基板(10)に形成した導電路(12
)のジャンピング接続が行われる。
Furthermore, by wire bonding the pad (42) formed on the sub-board (30) and the pad (18) formed on the mother board (10), the electronic circuit of the sub-board (30) and the mother board (10) are bonded. The interconnections of the electronic circuits are made, and the conductive paths (12) formed on the motherboard (10) are
) jumping connections are made.

既に明らかなように、本発明の混成集積回路装置はマザ
ー基板(10)上の所定位置にサブ基板(30)を離間
配置する基板構造を有するため、サブ基板(30)の固
着工程、サブ基板(30)上の導電路とマザー基板(1
0)上の導電路の相互接続工程はマザー基板(10)上
に固着される集積回路素子、あるいはチップ素子と同等
に行われ、ケーシングを除く製造、試験工程がマザー基
板(10)上で完了する。また、本発明の混成集積回路
装置は最終的にケース材(図示しない)により封止され
るが、従来のケース材の中空構造内に収納することがで
きる。
As is already clear, since the hybrid integrated circuit device of the present invention has a substrate structure in which the sub-board (30) is spaced apart from a predetermined position on the mother board (10), the fixing process of the sub-board (30), the sub-board (30) The conductive path on the motherboard (1
0) The interconnection process of the conductive paths above is performed in the same way as for integrated circuit elements or chip elements fixed on the motherboard (10), and the manufacturing and testing processes except for the casing are completed on the motherboard (10). do. Furthermore, although the hybrid integrated circuit device of the present invention is finally sealed with a case material (not shown), it can be housed within the hollow structure of a conventional case material.

以上本発明の一実施例を説明したが、本発明はサブ基板
の平面形状等に関して種々の変形が可能であって、実施
例に限定されるものではない。
Although one embodiment of the present invention has been described above, the present invention can be modified in various ways with respect to the planar shape of the sub-board, etc., and is not limited to the embodiment.

(ト)発明の効果 以上述べたように本発明の混成集積回路装置は(1)マ
ザー基板の導電路とサブ基板の導電路との相互接続を任
意の位置で行うことが可能なため導電路の引き回しによ
る実装面積の低下が回避される。
(G) Effects of the Invention As described above, the hybrid integrated circuit device of the present invention has the following advantages: (1) The conductive path of the mother board and the conductive path of the sub-board can be interconnected at any position; This avoids a reduction in mounting area due to routing.

(2)サブ基板の導電路によるマザー基板の導電路の長
スパンの接続が可能であるためジャンピング接続のため
のパッドが不要になり実装面積の低下が回避される。
(2) Since a long span of the conductive path on the mother board can be connected by the conductive path on the sub-board, pads for jumping connections are not required, and a reduction in the mounting area can be avoided.

(3)マザー基板、サブ基板共に金属基板を使用するた
め発熱素子の配置が自由である。
(3) Since metal substrates are used for both the mother board and the sub-board, the heating elements can be freely arranged.

(4)マザー基板上にサブ基板を離間固着するためマザ
ー基板の全領域を素子実装に使用できる。
(4) Since the sub-boards are spaced and fixed on the mother board, the entire area of the mother board can be used for mounting elements.

(5)サブ基板を、マザー基板に固着搭載した所定の集
積回路素子に隣接配置したため、その集積回路素子電極
をマザー基板のパッドにもサブ基板のパッドにも直接ワ
イアボンディングすることができ、ワイアボンディング
数が低減されると共に導電路面積が低減される。
(5) Since the sub-board is placed adjacent to a predetermined integrated circuit element fixedly mounted on the mother board, the integrated circuit element electrode can be directly wire-bonded to both the mother board pad and the sub-board pad. The number of bondings is reduced and the area of the conductive path is reduced.

(6)サブ基板とマザー基板の主面が同一方向に面する
ため、サブ基板とマザー基板の導電路の相互接続後の機
能試験、トラブルシューティングが容易である。
(6) Since the main surfaces of the sub-board and the mother board face in the same direction, it is easy to perform functional tests and troubleshooting after interconnecting the conductive paths between the sub-board and the mother board.

(7)集積回路としてチップ素子を使用するため高集積
度が達成される。
(7) A high degree of integration is achieved because chip elements are used as integrated circuits.

(8)サブ基板に加工が容易な銅合金を使用するため離
間固着のための支持部を一体成形することができる。
(8) Since a copper alloy that is easy to process is used for the sub-board, the supporting part for separating and fixing can be integrally molded.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の平面図、第2図は第1図の
I−1線断面図、第3図は本発明で使用されるサブ基板
の平面図、第4図は従来の混成集積回路装置の平面図。 10・・・マザー基板、12.36・・・導電路、14
.38.40.44・・パッド、  16−・−外部リ
ード用バンド、  18.42・−内部接続用パッド、
  20・・支持部材用パッド、  22.24.46
・・・集積回路素子、  30・・サブ基板、  32
・・・孔、  34・・・支持部材。
FIG. 1 is a plan view of an embodiment of the present invention, FIG. 2 is a sectional view taken along line I-1 in FIG. 1, FIG. 3 is a plan view of a sub-board used in the present invention, and FIG. 4 is a conventional FIG. 2 is a plan view of a hybrid integrated circuit device. 10...Mother board, 12.36...Conducting path, 14
.. 38.40.44...Pad, 16--Band for external lead, 18.42--Pad for internal connection,
20... Pad for support member, 22.24.46
... integrated circuit element, 30 ... sub-board, 32
...hole, 34...support member.

Claims (9)

【特許請求の範囲】[Claims] (1)第1の絶縁金属基板上に所定形状に導電路を形成
し、その導電路の所定位置に少なくとも集積回路素子を
固着搭載したマザー基板と、 第2の絶縁金属基板上に所定形状に導電路を形成し、そ
の導電路の所定位置に集積回路素子および、あるいはチ
ップ抵抗、チップコンデンサ等のチップ素子を固着搭載
したサブ基板とから構成され、 前記サブ基板を、マザー基板に固着搭載した所定の集積
回路素子に隣接配置したことを特徴とする混成集積回路
装置。
(1) A motherboard in which a conductive path is formed in a predetermined shape on a first insulated metal substrate, and at least an integrated circuit element is fixedly mounted on a predetermined position of the conductive path; It is composed of a sub-board on which a conductive path is formed and an integrated circuit element and/or a chip element such as a chip resistor or a chip capacitor is fixedly mounted on a predetermined position of the conductive path, and the sub-board is fixedly mounted on a mother board. A hybrid integrated circuit device characterized in that it is arranged adjacent to a predetermined integrated circuit element.
(2)前記所定の集積回路素子電極とサブ基板のパッド
をワイアボンディングしたことを特徴とする請求項1記
載の混成集積回路装置。
(2) The hybrid integrated circuit device according to claim 1, wherein the predetermined integrated circuit element electrode and the pad of the sub-substrate are wire-bonded.
(3)前記サブ基板高とマザー基板上に固着した前記所
定の集積回路素子の実装高とを略等しくしたことを特徴
とする請求項1記載の混成集積回路装置。
(3) The hybrid integrated circuit device according to claim 1, wherein the sub-board height and the mounting height of the predetermined integrated circuit element fixed on the motherboard are approximately equal.
(4)前記マザー基板の所要の導電路の接続をサブ基板
の導電路を介して行ったことを特徴とする請求項1記載
の混成集積回路装置。
(4) The hybrid integrated circuit device according to claim 1, wherein the required conductive paths on the mother board are connected via conductive paths on a sub-board.
(5)前記第2の絶縁金属基板を銅、あるいは銅合金で
形成したことを特徴とする請求項1記載の混成集積回路
装置。
(5) The hybrid integrated circuit device according to claim 1, wherein the second insulated metal substrate is made of copper or a copper alloy.
(6)前記サブ基板の端部を折り曲げ、あるいは基板端
部に形成したタブを折り曲げてサブ基板の支持部とした
ことを特徴とする請求項1記載の混成集積回路装置。
(6) The hybrid integrated circuit device according to claim 1, wherein an end of the sub-board is bent, or a tab formed at the end of the board is bent to serve as a support for the sub-board.
(7)前記サブ基板の面積を前記マザー基板に比較して
小面積としたことを特徴とする請求項1記載の混成集積
回路装置。
(7) The hybrid integrated circuit device according to claim 1, wherein the area of the sub-board is smaller than that of the mother board.
(8)前記サブ基板の所定の導電路と前記マザー基板の
導電路とをワイアボンディングしたことを特徴とする請
求項1記載の混成集積回路装置。
(8) The hybrid integrated circuit device according to claim 1, wherein a predetermined conductive path on the sub-board and a conductive path on the mother board are wire-bonded.
(9)前記集積回路素子にチップ素子を用いたことを特
徴とする請求項1記載の混成集積回路装置。
(9) The hybrid integrated circuit device according to claim 1, wherein a chip element is used as the integrated circuit element.
JP2228265A 1990-08-31 1990-08-31 Hybrid integrated circuit device Expired - Lifetime JP2828753B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2228265A JP2828753B2 (en) 1990-08-31 1990-08-31 Hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2228265A JP2828753B2 (en) 1990-08-31 1990-08-31 Hybrid integrated circuit device

Publications (2)

Publication Number Publication Date
JPH04111460A true JPH04111460A (en) 1992-04-13
JP2828753B2 JP2828753B2 (en) 1998-11-25

Family

ID=16873768

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2228265A Expired - Lifetime JP2828753B2 (en) 1990-08-31 1990-08-31 Hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JP2828753B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008141084A (en) * 2006-12-05 2008-06-19 Nec Electronics Corp Semiconductor device
JP2015534715A (en) * 2012-08-21 2015-12-03 エプコス アクチエンゲゼルシャフトEpcos Ag Device structure

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008141084A (en) * 2006-12-05 2008-06-19 Nec Electronics Corp Semiconductor device
JP2015534715A (en) * 2012-08-21 2015-12-03 エプコス アクチエンゲゼルシャフトEpcos Ag Device structure
US10278285B2 (en) 2012-08-21 2019-04-30 Epcos Ag Electric component assembly

Also Published As

Publication number Publication date
JP2828753B2 (en) 1998-11-25

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