JPH04111471A - Thin film transistor memory - Google Patents

Abstract

PURPOSE:To make it possible to shorten write in/erase time sharply and enlarge its scale by comprising a selection transistor so as to make available carrier conduction of both a p channel and an n channel and erasing memory by p channel operation and writing in memory by n channel operation. CONSTITUTION:This invention relates to stagger structure where a semiconductor layer 36 is staggered between a source electrode 32 and a drain electrode 34, and gate electrodes 39 and 40. The portions which include the selection electrode 40, the source electrode 32, the drain electrode 32, and a semiconductor layer 36 constitute a selection transistor Tr 11 while the portions which include the memory gate electrode 39, the source electrode 32, the drain electrode 34, and the semiconductor layer 36 constitute a memory transistor Tr 10. When phosphorous doped polysilicon (poly-Si) is used as ohmic contact layers 33 and 35, it is possible to write in or erase memory to any conduction of p channel operation and n channel operation which are characteristic of the performance of transistors.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention provides electrical writing and writing using thin film transistors.
The present invention relates to an erasable thin film transistor memory.

[Prior Art] Recently, a thin film transistor memory has been developed as a memory element such as an EEPROM, in which a memory thin film transistor and a selection transistor for selecting the memory thin film transistor are made of thin film transistors. This thin film transistor memory has a memory thin film transistor and a selection thin film transistor formed on an insulating substrate.The method of driving the memory cell is to operate the selection transistor in one channel, and write/erase by selecting/unselecting it. is being carried out.

[Problems to be Solved by the Invention] However, in such conventional thin film transistor memories, the selection transistor has one-side channel operation (
For example, since the configuration was such that writing/erasing was performed by selecting/unselecting the selected transistor, electron conduction was performed in the memory insulating film of the semiconductor layer by turning on the n-channel of the selected transistor. Writing to inject electrons into the memory takes a short time (on the order of 1 ms when the electric field between the memory gate and drain is set to 2 μV/cm)
However, for erasing that requires hole injection, even if the n-channel is turned on and the source/drain electric field reaches the memory area, it will take a long time (1 at 2 μV/cm).
The disadvantage is that a sec order) is required.

SUMMARY OF THE INVENTION An object of the present invention is to provide a thin film transistor memory using thin film transistors that can significantly shorten write/erase time and can be scaled up.

[Means for Solving the Problems] In order to achieve the above object, the thin film transistor memory according to the present invention includes a semiconductor layer, a source electrode and a drain electrode electrically connected to the semiconductor layer, and controls selection/non-selection of writing. A thin film transistor memory comprising a selection gate electrode to which a selection voltage is applied to move a predetermined carrier, and a memory gate electrode to which a gate voltage to move a predetermined carrier is applied, the selection gate electrode, the source electrode and the drain electrode , and the semiconductor layer is configured to perform both n-channel and n-channel carrier conduction, and is configured to erase the memory in n-channel operation and write to the memory in n-channel operation. This is what I did.

[Operation] According to the above-described means, the thin film transistor memory is configured such that the selection transistor is capable of carrying out both n-channel and n-channel carrier conduction, so that the selection transistor can be operated in both n-channel/n-channel directions. The n-channel erase/n-channel write mode can be used so that the state transition time is shortened in both write/erase modes, and the write/erase pulse application time can be shortened.

[Example code] Hereinafter, the present invention will be explained based on the drawings.

five star stars First, the present invention will be explained in detail.

The basic structure of a CMOS device is shown in FIG. CM
In an OS device, a large P+ diffusion layer, that is, a region called a p-well, is formed on an N-type substrate IO by diffusion of boron (B), etc., and an n-channel transistor Tr is formed in the region by diffusion of phosphorus (P). ,
A p-channel transistor Tr is formed on an N-type substrate 10 by boron diffusion or the like, and necessary portions are connected with a conductor such as aluminum. In the figure, 12.13 is the source/drain diffusion layer of the p-channel transistor Tr, I4
15 and 16 are the source/drain diffusion layers of the n-channel transistor Tr, and 17 is the gate electrode thereof. Therefore, n channels, n
Since channels are made in different areas using separate processes, the process is complicated and it is disadvantageous for integration. In addition, leakage current between the N-type substrate 10 and the source/drain diffusion layer is prevented by operating the PN junction with a reverse bias. Even if a channel is formed, it is not possible to apply a positive bias to the drain made of a p-type diffusion layer and move it into a transistor. That is, conventional transistors on Si substrates are essentially capable of only one-sided channel operation.

Therefore, the present invention aims to improve the performance of thin film transistor memories by realizing a thin film transistor that can operate in both n-channel/n-channel directions. To achieve this purpose, we will adopt the following basic structure.

(2) By using TPT on an insulating substrate, leakage current between the substrate and the substrate can be ignored.

■In the ohmic contact area with the source/drain electrode, impurities such as phosphorus, which do not act as a barrier against bias in the positive and imaging direction, have extremely weak rectification properties and have sufficient ohmic properties with metals. Doped poly-
3i layer is used.

(2) A semiconductor layer is sandwiched between the source/drain and the gate, and the structure is such that both p-channel and n-channel carriers are generated depending on the strength and direction of the electric field applied between the gate and the source/drain.

■By using a poly-Si layer close to an intrinsic semiconductor as the semiconductor layer, the Fermi level is close to the center of the band gap, and the band gap is narrow.
To be able to reach a voltage level that is practical for using both n-channels.

FIG. 2 is a sectional view of a poly-5i TFT having a staggered structure formed by the above basic structures (1) to (2).

In this figure, reference numeral 20 denotes a selection transistor with a staggered structure. a channel semiconductor layer 26 formed on the insulating substrate 21 on which the source electrode 22 and the drain electrode 23 are formed, and a gate insulating film 27 formed on the channel semiconductor layer 26. and,
A gate electrode 28 is formed on a gate insulating film 27. Also, an ohmic contact layer 24 formed on the source electrode 22 and the drain electrode 23.
25 is a contact layer through which both P and N type carriers can flow regardless of whether the dopant is P type or N type;
For example, p.

It is formed of an ohmic contact semiconductor layer such as 1y-3i or a (amorphous)-3i.

FIG. 3 is a diagram showing the VG-ID (gate voltage-drain current) characteristics of the selection transistor 20, with the drain voltage Vd being 5V, IOV, and 15V.

It shows an n-channel operation and an n-channel operation when the voltage is set to 20V (however, the source voltage Vs is set to the ground level). As the drain voltage Vd increases, saturation occurs, but on the n-channel side, the third
It is represented by a single line with overlapping graphs, like the thick solid line in the figure. Also, on the n-channel side, Id
is gradually shifting. On the other hand, contrary to the above case, V
When d is set to the negative side, the n-channel side operates as shown on the left side of the figure, and in this case also, the n-channel side is represented by a single line. As shown in FIG. 2, since the selection transistor 20 has three terminals, the subthreshold voltage Vthn for n-channel operation is determined by the relationship between the low side voltage of the source and drain and the gate voltage Ve.
The subthreshold voltage Vthp for n-channel operation is determined by the relationship between the higher voltage between the source and drain and the gate voltage. An equivalent circuit of the selection transistor 20 at this time is shown in FIG.

Also, by increasing the drain voltage Vd, poly -3
When a voltage higher than the bandgap of i is applied between the source and drain, n-channel and n-channel bidirectional operation is observed, and the channel current continues to flow at any gate voltage (see Figure 3).

5 and 6 are diagrams showing the Vd-Id (drain voltage-drain current) characteristics during n-channel and n-channel operation, and FIG. 5 shows the Vd-Id characteristics on the n-channel side, and The figures each show the Vd-Id characteristics on the n-channel side. As shown in Figures 5 and 6, although there is a slight barrier effect on the source-drain electric field of the n+ diffusion layer on the n-channel side, both n-channel and n-channel can perform practical transistor operation from a low Vd. I know that there is.

In this way, one thin film transistor is n-channel, n-channel
Since the channel operates in both directions, there is no need to make separate n-channel transistors and n-channel transistors, so if a 0M03 circuit that requires both n-channel and n-channel operations, for example, is manufactured using this thin film transistor, the manufacturing process will be simplified and highly integrated. will be promoted. Furthermore, since it is a three-terminal element and does not have a fixed potential called substrate potential, it is possible to lower the voltage when performing n-channel and n-channel bidirectional operation. For example, drain voltage Vd
is IOV, the source voltage Vs is OV%, the subthreshold voltage Vthp for P-channel operation is -10V, and the subthreshold voltage Vthn for n-channel operation is 5V, as shown in FIG. In a conventional CMO3 structure transistor with a substrate potential, if bidirectional operation is to be performed, a low potential power supply of -10 V or less is required on the p-channel operation side.

On the other hand, in the case of the thin film transistor 20 which has no substrate potential, even when performing p-channel operation, it is possible to perform both p-channel/n-channel operation by appropriately setting gate bias conditions, etc. It is possible to realize this without using .

If the thin film transistor 20 having the above characteristics is applied to a selection transistor of a memory, n-channel conduction can be used for charging (electron injection) and p-channel conduction can be used for erasing (hole injection). Examples will be described below based on the above principle.

8 to 18 are diagrams showing an embodiment of the thin film transistor memory according to the present invention, and FIGS. 8 to 12 are manufacturing process diagrams of the thin film transistor memory.

This embodiment shows an example employing a staggered structure in which a semiconductor channel layer is sandwiched between a source/drain electrode and a gate electrode.

First, as shown in FIG. 8, a conductive layer made of, for example, chromium (Cr) and an n-type polysilicon (poly-silicon) doped with phosphorus (P) or arsenic (As) are formed on an insulating substrate 31 made of glass or the like. A source electrode 32 and its contact layer 33 are formed by sequentially depositing an ohmic contact layer such as S i ) by sputtering or the like, and patterning the source electrode 32 and its contact layer 33.
A drain electrode 34 and its contact layer 35 are formed.

In this case, phosphorus-doped polysilicon (poly-
When S i ) is used as the ohmic contact layer 33, 35, write/erase operations as a memory can be performed for both p-channel operation and n-channel operation, which are the operating characteristics of a transistor.

Next, an amorphous silicon (A-3i) layer is formed on the insulating substrate 31 on which the source electrode 32, the drain electrode 34, and the contact layer 33. Also silicon atom Si
By increasing the amount of silicon nitride, which has a charge storage function,
(After about 100 layers have been deposited, patterning is performed to form a semiconductor layer 36 as shown in FIG. 9, and a memory nitride film 37 is further formed in the center of the semiconductor layer 36 as shown in FIG. 10.

Next, as shown in FIG. 11, a memory gate insulating film 38a made of stoichiometric silicon nitride is deposited over the entire surface of the semiconductor layer 36 on which the memory nitride film 37 has been formed, and a conductive film such as chromium is deposited thereon. After the layers are deposited, they are patterned to form the memory gate electrode 39 of the memory transistor Trio. In this case, the memory gate electrode 39 is formed at a position facing the memory nitride film 37.

Next, as shown in FIG. 12, the memory gate electrode 39
A selection gate insulating film 3 made of silicon nitride in a stoichiometric ratio is formed over the entire surface of the memory gate insulating film 38a on which the memory gate insulating film 38a is formed.
Form 8b. After that, this memory gate insulating film 38
A conductive layer made of chromium or the like is deposited on the conductive layer b by sputtering or the like and patterned to form a selection gate electrode 40 to complete a thin film transistor memory.

Thin film transistor memory 5 manufactured as described above
0 is a thin film transistor having four terminals: a source electrode 32, a drain electrode 34, a memory gate electrode 39, and a selection gate electrode 40, and a semiconductor layer is provided between the source electrode 32 and drain electrode 34 and the gate electrode 39.40. It has a staggered structure with 36 in between. Then, the selection gate electrode 40. Source electrode 32, drain electrode 34
and a portion including the semiconductor layer 36 is a selection transistor Trl.
A memory gate electrode 39, a source electrode 32,
A portion including the drain electrode 34 and the semiconductor layer 36 constitutes a memory transistor Trio. In other words, this thin film transistor memory 50 has a staggered structure selection transistor T on a staggered structure memory transistor TrlO.
It has a structure in which rlls are stacked.

FIG. 13 is a diagram showing the VG-ID (gate voltage-drain current) characteristic of the selection transistor Trl 1 of the thin film transistor memory 50 in which the memory transistor TrlO and the selection transistor Tri 1 are configured as one memory cell, and the drain voltage Vd 5V, IOV, 15V, 2
0Vl: This shows the characteristics when the voltage is 0Vl. The selection transistor Trll can use either holes or electrons as carriers depending on the direction of the electric field between the selection gate electrode 40, the source electrode 32, and the drain electrode 34, so that an n-channel current or an n-channel current can be used depending on the value of the gate voltage vG. It has characteristics. In this case, since phosphorus-doped polysilicon (poly-S i ) is used as the ohmic contact layer 33, 35, there is a layer that does not become a barrier to the extent that it impedes conduction for either n-channel/n-channel conduction. can get. Therefore, as described below, depending on the gate bias conditions, n-channel/n
The structure allows conduction in both channels and allows for easy selection/non-selection operation.

FIGS. 14 and 15 show this selection transistor Trll.
An electric field strength of 2 μv/ClTl is applied between the source electrode 32 and drain electrode 34 and the memory gate electrode 39 using the selected gate voltage ■
Fig. 14 is a diagram showing the results of investigating how it changes depending on cG, and Fig. 14 shows the time required for the erasure transition, and Fig. 15
The figures each show the time required for write transition.

In the figure, the solid lines labeled 1, 2, 3, 4, and 5 are 100 μs, 1 ms, and 1, respectively.
0ms.

It shows a pulse width (application time) of 100+ns and 1 sec, and when the selection gate electrode Vcc is negative, n-channel conduction occurs, and when it is positive, n-channel conduction occurs. The peak portions shown in FIGS. 14 and 15 are n-channel.

This is a region where no n-channel current flows and it takes time for the electric field applied to the memory to reach the memory, and this region is used as a non-selection voltage during driving. Looking at FIGS. 14 and 15 from this point of view, it can be seen that writing is faster when the selection transistor operates as an n-channel, and conversely, erasing is faster when the selection transistor is operated as an n-channel. The reason why the non-selection voltage differs between writing and erasing is that a positive electric field is applied under the gate electrode after erasing, so V c − during writing
This is because Vd corresponds to the n-channel side in FIG. 13, and since a negative electric field increases under the gate electrode after writing, the n-channel side in FIG. 13 corresponds during erasing.

FIGS. 16(A) and 16(B) show equivalent circuits of the thin film transistor memory manufactured as described above, and this equivalent circuit consists of a selection transistor Trll and a memory transistor TrlO as shown in FIG. 16(B). This represents a structure in which these are connected in series. In other words, the thin film transistor memory of the present invention has a structure in which a staggered selection transistor Trll is stacked on a staggered memory transistor Trio, but the electrical operation of the memory transistor is as shown in FIG. 16(B). Tr
io and the selection transistor Trll are connected in series.

FIGS. 17 and 18 are diagrams showing the write mode/erase mode constructed based on the thin film transistor memory described above, and are represented by the equivalent circuit shown in FIG. 16(A). Note that 5o is the thin film transistor memory described above.

In the case of writing, as shown in FIG. 17, the thin film transistor memory 50 ((1-
1)) is connected to the memory gate line 51 connected to Vp.
/2 and an n-channel ON voltage is applied to the selection gate line 52, and Vp is applied to the memory gate line 53 to which the unselected thin film transistor memory 50 is connected.
/2 and a write non-selection voltage (for example, 10 .mu.) are applied to the selection gate line 54, respectively. In addition, -Vp/2 is applied to the data line 55 to which the write selection thin film transistor memory 50 (see (1-1) in the same figure) is connected, and -Vp/2 is applied to the data line 56. The same potential Vp/2 is applied to the data lines 57 and 58 to which the thin film transistor memory 50 is connected. Then, Vp/2 is applied to the selection gate line 52 (the n-channel of the selection transistor Trll is turned on), and -Vp/2 is applied to the data line 56 to which the drain of the selection transistor Trll is connected, thereby turning on the selection transistor Trll. is in a selected state and the writing of the thin film transistor memory 50 shown in FIG.
(electron e-injection) is performed.

On the other hand, in the thin film transistor memory 50 (see (2-1) in the same figure) connected to the same data line 55, 56, a write non-selection voltage is applied to the selection gate line 54 connected to this thin film transistor memory 50. (n-channel of selection transistor Trll is set to 0FF), so the selection transistor Trll is in a non-selected state and writing is prohibited. In this case, the memory transistor Trl of the thin film transistor memory 50 shown in FIG.
By increasing the electric field strength Vp between the memory gate electrode 40 and the source/drain with a selection gate bias so as to increase the channel impedance of the selection transistor Tr11, a high voltage Vp is effectively applied to both ends of the memory nitride film 37. It maintains the previous memory state by preventing the application of electric fields.

In addition, the thin film transistor memory 50.50 connected to the data line 57.58 ((1-2) (2-2) in the same figure)
) is the thin film transistor on the selected line, but is not written as data, and the voltage applied to the data line 57, 58 is the same as the voltage applied to the memory gate line 53 (Vp/2). Since the selection transistor Trll is at the potential, the selection transistor Trll is forcibly turned off, and the previous data is held in the memory transistor Trio.

Therefore, the thin film transistor memory 50 ((1-1) in the same figure)
(Reference) will be written to.

In the case of erasing, as shown in FIG. 18, the film transistor memory 50 to be erased (see (1-1) in the same figure)
-Vp/2 to the memory gate line 51 connected to
A p-channel ON voltage is applied to each selection gate line 52, and unselected thin film transistor memories 5
0 is connected to the memory gate line 53, and the selection gate line 54 is set to the erase non-selection voltage (for example, 1
5V) respectively. In addition, Vp/2 is applied to the data line 55 to which the erase-selected thin film transistor memory 50 (see (1-1) in the same figure) is connected, and Vp/2 is applied to the data line 56. Data line 57 to which memory 5° is connected.
The same potential -Vp/2 is applied to each of the terminals 58 and 58. Then, the potential difference between the gate and source of the thin film transistor memory 50 connected to the memory gate line 51 to be erased becomes Vp, and the line is erased all at once (the holes h+ are trapped in the memory nitride film 37).

In addition, for the thin film transistor memory in the portion that is not desired to be erased, the memory gate line 53 has the same potential as the data lines 55 to 58 at Vp/
2 is applied and the potential difference becomes 0, so it will not be erased.

As explained above, since the selection transistor Tril is operated in both p-channel/n-channel directions, the p-channel erase/n-channel write mode is set to shorten the state transition time in both write/erase modes. becomes possible to use. As a result, the write/erase pulse application time becomes shorter, so the selection transistor Tr
The non-selective characteristic that prevents the application of pulses to the memory by turning off ll is also improved, and data can be written and erased correctly in each cell, making it possible to perform large-scale EEP.
It is suitable for use as a ROM.

Note that the materials of the selection gate electrode, ohmic contact layer, and semiconductor layer in the above embodiments are merely examples, and it goes without saying that other materials having the same or similar properties can be used.

In addition, although the above embodiment is an example in which the semiconductor channel layer is sandwiched between the source/drain electrode and the gate electrode and is applied to a selective transistor memory with a staggered structure, the stacked structure may be reversed. It is applicable to all other structures such as the reverse staggered structure.

[Effects of the Invention] According to the present invention, a thin film transistor memory including a selection gate electrode, a source electrode/drain electrode, and a semiconductor layer performs both p-channel and n-channel carrier conduction operations,
Since the structure is configured such that the memory is erased by the n-channel side operation and the memory is written by the n-channel side operation, the write/erase time can be shortened by applying an electric field directly to both ends of the memory insulating film. In particular, the transition time during erasing, which requires hole injection, can be significantly shortened. Therefore, since the write/erase pulse application time is shortened, the non-selection characteristic that prevents pulse application to the memory by setting the selection transistor to FF is also improved.
Data can now be written and erased correctly in each cell, making it possible to use it as a large-scale EEPROM.

Furthermore, since one transistor can operate in both p-channel and n-channel directions, there is no need to create separate n-channel transistors and n-channel transistors, which simplifies the manufacturing process and allows for higher integration and larger area. will be realized. This makes it possible to use not only select transistor memory but also memory cells that require both p-channel/n-channel operation
It can also be applied to circuits similar to MOS circuits.

[Brief explanation of the drawing]

1 to 7 are diagrams for explaining the principle of the thin film transistor memory according to the present invention. FIG. 1 is a diagram showing a conventional 0MO3 structure for explaining the principle, and FIG. 3 is a Ve-Io characteristic diagram of a thin film transistor, FIG. 4 is an equivalent circuit diagram of a thin film transistor, FIG. 5 is a Vd-Id characteristic diagram of the n-channel side of a thin film transistor, and FIG. 6 is a cross-sectional diagram of a Si selection transistor. A Vd-Id characteristic diagram on the n-channel side of a thin film transistor, FIG. 7 is a diagram for explaining the low voltage operation of a thin film transistor that operates in both directions, and FIGS. FIG. 8 is a diagram illustrating an example.
Figure 12 is a manufacturing process diagram of a thin film transistor memory.
Figure 3 is a VG-I f) characteristic diagram of the thin film transistor memory, Figure 14 is a characteristic diagram showing the time required for erasure transition,
Fig. 15 is a characteristic diagram showing the time required for write transition, Fig. 16 is an equivalent circuit diagram of a thin film transistor memory, and Fig. 17 is a characteristic diagram showing the time required for write transition.
18 is a circuit diagram for explaining the write mode operation of the thin film transistor memory, and FIG. 18 is a circuit diagram for explaining the erase mode operation of the thin film transistor memory. 20... Thin film transistor, 21.31... Insulating substrate, 22.32... Source electrode, 23°34
...Drain electrode, 24.25...High concentration doping layer, 26.36...Semiconductor layer for channel, 2
7... Gate insulating film, 28... Gate electrode, 3
6...Semiconductor layer, 37...Memory nitride film, 38
...Gate insulating film, 38a...Memory gate insulating film, 38b...Selection gate insulating film, 39...
Memory gate electrode, 40...Selection gate electrode, 50
...Thin film transistor memory. Figure 3 Vd>0 Patent Applicant Casio Computer Co., Ltd. Figure 1 GCv] Figure 16 Figure 17

Claims (1)

[Claims] A semiconductor layer, a source electrode and a drain electrode electrically connected to the semiconductor layer, a selection gate electrode to which a selection voltage is applied to control selection/non-selection of writing, and a predetermined carrier. A thin film transistor memory comprising a memory gate electrode to which a gate voltage is applied to move p.
A thin film transistor memory characterized in that it is configured to allow carrier conduction in both channel and n-channel, and is configured to erase the memory using p-channel operation and write to the memory using n-channel operation.