JPH04111476A - Manufacture for compound semiconductor device - Google Patents

Abstract

PURPOSE:To provide a flat formation of an InGaAs third compound semiconductor layer having a small, band gap and at the same time, prevent a contact between the third compound semiconductor layer and a dielectric film, e.g. an SiN film, by providing a second compound semiconductor layer serving as a mask with a canopy by making use of the side etching of a first compound semiconductor layer in a photodiode formation of a planar construction. CONSTITUTION:A recessed portion provided in a first compound semiconductor layer 13 is expanded by a side etching and there, an InGaAs third compound semiconductor layer 22 having a small band cap is embedded for growing a crystal. This enables the third compound semiconductor layer to be formed into a flat regrowth layer on conditions that no unusual growth comes about. Namely, of significance is that a second compound semiconductor layer 14 provided on the first compound semiconductor layer 13 is protruding as a canopy. Also, even in the growth of a fourth compound semiconductor layer 23, no unusual growth occurs by virtue of the canopy effect of a SiN film 15.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention relates to a manufacturing technology for semiconductor devices such as light emitting elements and light receiving elements used in optical communication, and particularly relates to a manufacturing technology for semiconductor devices such as light emitting elements and light receiving elements used in optical communication. The present invention relates to a method for manufacturing a compound semiconductor device including a step of embedding a semiconductor layer.

(Prior Art) In recent years, compound semiconductor devices using compound semiconductors have been developed as optical semiconductor elements such as light emitting elements and light receiving elements used in optical communication. This device utilizes light emission and light reception phenomena by applying a bias to a pn junction of a compound semiconductor, and is desired to have higher performance as information processing speed increases. In particular, there are strong demands regarding high-speed response characteristics and reliability, and research and development have been actively conducted in recent years.

In order to simultaneously ensure high-speed response characteristics and reliability, it is necessary to create a Brenna structure using a regrowth technique in which crystal growth is divided into two steps. At this time, reducing the leakage current of the element is an essential element for improving the performance of the compound semiconductor device.

FIG. 3 is a cross-sectional view showing a schematic configuration of a conventional light receiving element having a planar structure. 1 in the figure is a semi-insulating InP substrate,
A dielectric film 2 made of SiN or the like having a partial opening is formed on this substrate 1, and a substrate 1 using this dielectric film 2 as a mask is formed.
A recess is formed by etching. Then, an n-type InP crystal layer 3. InGaAs mixed crystal layer 4
and p-type! An nP crystal layer 5 is grown and formed. Also,
A ring-shaped electrode 6 is provided near the opening of the dielectric film 2, and an electrode 7 is provided on the lower surface of the substrate 1.

In this configuration, by applying a reverse bias between the electrodes 6 and 7, the InGaAs layer 4 acts as a light absorption layer and operates as a photodiode.

However, this type of device has the following problems. That is, I with small bandgap energy
Since the nGaAs layer 4 and the dielectric SiN film 2 are in contact with each other, a leakage current is generated through the interface state of the SiN film 2.
live. This leakage current causes a reduction in receiving sensitivity, which can be fatal to photodiodes. Further, in a laser diode having a semi-insulating 1nP layer inside the element, there is a problem in that leakage current of the element deteriorates the oscillation threshold.

(Problems to be Solved by the Invention) Conventionally, when a planar structure photodiode or the like is created using a two-step crystal growth technique, problems arise due to contact between a compound semiconductor layer with a small band gap and a dielectric film. There was a problem in that leakage current of the element occurred.

The present invention has been made in consideration of the above circumstances, and its purpose is to eliminate leakage current in an element caused by contact between a compound semiconductor layer with a small band gap and a dielectric film, and to An object of the present invention is to provide a method for manufacturing a compound semiconductor device that can improve characteristics.

[Structure of the Invention] (Means for Solving the Problems) The gist of the present invention is to prevent contact between a compound semiconductor layer with a small band gap such as InGaAs and a dielectric film such as SiN.

That is, the present invention provides a method for manufacturing a compound semiconductor device such as a light emitting element or a light receiving element, in which a first compound semiconductor layer (for example, InGaAsP) and a second compound semiconductor layer (for example, InP) are formed on a compound semiconductor substrate such as InP. After the sequential growth, a dielectric film (for example, 5iN) having a partial opening is formed on the second compound semiconductor layer, and then the second compound semiconductor layer is selectively etched using the dielectric film as a mask. Side etching is performed on the second compound semiconductor layer, selectively etching the first compound semiconductor layer using the remaining second compound semiconductor layer as a mask, side etching is performed on the first compound semiconductor layer, and then the first compound semiconductor layer is side etched. A third compound semiconductor layer (for example, InGaAs) is grown on the etched portion of the second compound semiconductor layer, and then a fourth compound semiconductor layer (for example, InP) is grown on the etched portion of the second compound semiconductor layer. This is how I did it.

(Function) According to the present invention, a recess provided in the first compound semiconductor layer is widened by side etching, and a third compound semiconductor layer such as InGaAs having a small band gap is buried therein and crystal grown. In this way, it becomes possible to form a flat regrown layer under conditions that do not cause abnormal growth of the third compound semiconductor layer. This was confirmed through experiments, and the important point is that the second compound semiconductor layer provided on the first compound semiconductor layer functions as a mask and protrudes. This second compound semiconductor layer is effective in preventing leakage current, and a compound semiconductor device with excellent characteristics is realized.

Also, in the growth of the fourth compound semiconductor layer, abnormal growth does not occur because the dielectric mask protrudes due to side etching of the second compound semiconductor layer. Therefore,
A Brehner-type compound semiconductor device without a step on the element surface can be manufactured by a simple method.

(Example) Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.

FIG. 1 is a sectional view showing the manufacturing process of a photodiode according to a first embodiment of the present invention.

First, as shown in FIG. 1(a), an n-type 1nP substrate 11
An n-type InP buffer layer 12 is grown thereon to a thickness of 2 μm, and then an n-type InGaAsP layer (first compound semiconductor layer) 13 is grown to a thickness of 2 μm, and an n-type InP layer (second compound semiconductor layer) is grown to a thickness of 2 μm. A layer) 14 is grown to a thickness of 1 μm.

As for the formation method of each layer, it is possible to grow crystals with extremely high precision by a chemical vapor deposition method (MOCVD method) using an organic metal. The above is configured as a base. Thereafter, a SiN film (dielectric film) 15 is formed on the main surface of the base body to a thickness of 0.2 μm by plasma CVD, and then patterned to form, for example, a rectangular opening.

Next, using an HCl-based etching solution, as shown in FIG. 1(b)
As shown in FIG. 3, the InP layer 14 is selectively etched using the SiN film 15 as a mask to form a first recess. At this time, I
Side etching is performed to match the thickness of the nP layer 14 and the width of the path. That is, the end of the SiN film 5 is made to protrude like a canopy.

Thereafter, using the remaining InP layer 14 as a mask, the InGaAsP layer 13 is selectively etched with a sulfuric acid-based etching solution to form the second four parts. At this time, the edge of the InP layer 14 is etched with InGaA by side etching.
The sP layer 13 is made to protrude like an eave with a thickness of about 3 layers.

Next, as shown in FIG. 1(c), an InGaAsP uneven layer 21 is selectively grown in the second interlayer 3 of the InGaAsP layer 13. Then, as shown in FIG. InGaAsP buffer layer 2
1 is formed along the bottom surface of the second four parts with a thickness of 0.5 μm. As this buffer layer 21, an InP layer may be formed. Next, n is deposited on the InGaAsP buffer layer 21.
The type InGaAs layer (third compound semiconductor layer) 22 is 1.
It is grown and formed to a thickness of 5 μm. At this time, InGaAs
In the layer 22, a flat selective crystal growth layer is obtained without abnormal crystal growth due to the overhang of the InP layer 14. Next, a p-type InP layer (fourth
The compound semiconductor jW) 23 is selectively crystal grown. InP
The layer 23 is formed flat with a thickness of 1 μm so as to fill the first recess. Even in this case, abnormal crystal growth is prevented by the effect of the canopy of the SiN film 15. In the manner described above, selective crystal growth is completed.

Next, as shown in FIG. 1(d), p is applied to the main surface side of the base.
A type ohmic electrode 31 is formed by vapor deposition of TiPtAu and patterned. At this time, the SiN film 15 is placed so that the electrode 31 completely covers the opening of the SiN film 15
Process it into a rectangle that is slightly larger than the opening in step 5. Furthermore, an n-type ohmic electrode 32 is formed on the back side of the base by vapor deposition of AuGe.

The thus manufactured photodiode has an InP layer 12
．． The InGaAsP layer 13 sandwiched between the InGaAsP layer 14 and the InGaAsP layer 13 are sandwiched between the three waveguide layers, and the InGaAsP layer 13 is sandwiched between the three waveguide layers.
Optical information is detected by absorbing it in the S layer 22. In this case, the SiN film 15 as a dielectric film and the InGaAs layer 22 having a small band gap energy do not come into direct contact with each other, so that leakage current can be reduced. According to experiments conducted by the present inventors, the leakage current value in the photodiode of this example is approximately f/1 of that of the conventional structure.
It was found that the light-receiving sensitivity was significantly improved.

FIG. 2 is a sectional view showing the manufacturing process of a laser diode according to a second embodiment of the present invention.

First, as shown in FIG. 2(a), an n-type 1nP substrate 41
N type on top! An nP buffer layer 42 is formed to a thickness of 2 μm, and an n-type InGaAsP layer 43 is formed thereon to a thickness of 1 μm. Next, the n-type InGaAsP layer 43 has a smaller band gap energy than the n-type InGaAsP layer 43.
layer or multi-quantum well structure active layer 44 with a thickness of 0.1 μm.
Form to a thickness of . After that, a p-type 1 layer having the same bandgap energy as the n-type I nGaAs P layer 43 is formed.
An nGaAsP layer 45 is formed to a thickness of 1 μm, and a p-type InP layer 46 is formed thereon to a thickness of 0.6 μm. As for each formation method, it is possible to grow crystals with extremely high precision using the MOCVD method. The above is configured as a base. Then, the main surface of the substrate is coated with 5
After forming the i02 film 47 to a thickness of 1 μm, it is patterned to leave it in a rectangular shape, for example.

Next, using an HCl-based etching solution, as shown in FIG. 2(b)
As shown in FIG. 3, the InP layer 46 is selectively etched as the film edge 7 of the SiO2 film 47 to form the first four parts. At this time, side etching is performed with a width such as between the InP layer 46 and the path, so that the film end 7 of the SiO2 film 47 protrudes like a canopy. Subsequently, using the remaining InP layer 46 as a mask, the InGaAs P layers 43, 44.degree. 45 are selectively etched using a sulfuric acid-based etching solution to form a second recess.

At this time, by side etching, all InGaAs
An eaves of the p-type 1 n P layer 46 having a width equivalent to the thickness of the P layers 43 to 45 is formed.

Next, as shown in FIG. 2(e), a semi-insulating 1nP buried layer 61 is selectively crystal-grown in the second recess. A semi-insulating 1nP buried layer 61 with a thickness of 2 μm is formed along the bottom surface of the second four parts.

A high resistance InP layer may be formed as this buried layer 61. Subsequently, an n-type InP layer 62 is formed on the semi-insulating InP buried layer 61 to a thickness of 1 μm. Here, the semi-insulating InP layer 61 does not grow abnormally due to the eaves of the p-type InP layer 46 and a flat selective crystal growth layer can be obtained, and the n-type I
The nP layer 62 is similarly formed flat.

Next, as shown in FIG. 2(d), after removing the 5in2 film 47, a p-type InP layer 71 with a thickness of 1 μm is formed on the main surface of the substrate. Subsequently, a p-type ohmic electrode 72 is formed on the p-type 1nP layer 71 by vapor deposition of TiPtAu, and an n-type ohmic electrode 73 is formed on the lower surface of the substrate 41.
It is formed by vapor deposition of uGe.

The thus manufactured laser diode is made of semi-insulating In
The leakage current through the P layer 61 was reduced to about 1/1O compared to the conventional one, demonstrating excellent characteristics with a low threshold current.

Here, in the conventional method, a p-type 1 nGaAs P layer 45
A dielectric film is directly formed thereon, and the InGaAsP layer 45.44° 43 is mesa-etched using this dielectric film as a mask. After forming InP layers 61 and 62, the dielectric film is removed, and then an InP layer 71 is formed. In this case, in the step of removing the dielectric film, the crystal growth layer is exposed to air, causing contamination. In particular, InGaAsP
The interface between the layer 45 and the InP layer 61 is exposed, and deterioration of the interface occurs when the InP layer 71 is formed. This interface deterioration is due to crystal dislocation and generation of interface states, and this deterioration phenomenon adversely affects even the active layer 44 located at a short distance. That is, the generation of dislocations or interface states results in leakage current via what is generally called a deep center (a deep level in a semiconductor band gap). This leakage current causes deterioration of the semiconductor laser, resulting in extremely poor reliability. In this embodiment, since the interface between the InGaAsP layer 45 and the InP layer 61 is not exposed when the dielectric film 47 is removed, there is no leakage current due to the above factors.

Note that the present invention is not limited to the embodiments described above. In the first embodiment, optical information is detected by guiding light into the first compound semiconductor layer from the lateral direction.
By using a ring-shaped electrode as the upper electrode, it is also possible to detect light from above as in the conventional case.

Further, the compositions of the first to fourth compound semiconductor layers are not limited to those in the embodiments, but can be changed as appropriate according to specifications. In addition, without departing from the gist of the present invention,
Various modifications can be made.

[Effects of the Invention] As described in detail above, according to the present invention, by providing a canopy on the second compound semiconductor layer serving as a mask by utilizing side etching of the first compound semiconductor layer, InGa
A third compound semiconductor layer such as As having a small band gap can be formed flat. Therefore, it is possible to prevent contact between the third compound semiconductor layer and a dielectric film such as SiN, and thereby it is possible to realize a compound semiconductor device with low leakage current even if selective crystal growth is used. becomes.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing the manufacturing process of a photodiode according to the first embodiment of the present invention, FIG. 2 is a cross-sectional view showing the manufacturing process of a laser diode according to the second example of the present invention, and FIG. The figure is a sectional view showing the schematic structure of a conventional device. 11-n-type InP substrate, 12...n-type 1nP buffer layer, 13 =-n-type 1nGaAs P layer, 14---n
type InP layer, 15...SiN film (dielectric film), 21--n-type InP layer, 22.=InGaAs layer, 23...p
type InP layer, 31... n-side electrode, 32... n-side electrode.

Claims (1)

[Claims] a step of sequentially growing first and second compound semiconductor layers on a semiconductor substrate; a step of forming a dielectric film having a partial opening on the second compound semiconductor layer; selectively etching the second compound semiconductor layer and side etching the second compound semiconductor layer; selectively etching the first compound semiconductor layer using the remaining second compound semiconductor layer as a mask; A step of performing side etching on the first compound semiconductor layer, a step of growing and forming a third compound semiconductor layer on the etched portion of the first compound semiconductor layer, and a step of forming a fourth compound semiconductor layer on the etched portion of the second compound semiconductor layer. A method for manufacturing a compound semiconductor device, comprising the step of growing and forming a compound semiconductor layer.