JPH0411363A - Mark detection device in information recording and reproducing device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a detection circuit for special marks such as lid marks on optical discs and the like.

[Prior Art] An optical disk has tracks formed in a spiral shape on the medium, and each track is further divided into recording units called sectors. When recording information on such a medium or reproducing information from the medium, it is necessary to attach a mark indicating the starting point for each sector, which is about one recording rate.

This is commonly called a sector mark. In addition to this, sector marks are also used to generate various timings associated with reading and writing, so their pressure detection reliability must be sufficiently high.

As a method for detecting such sector marks, Japanese Patent Application Laid-Open No. 58-1
There is one described in 69337 gazette.

Hereinafter, eight conventional sector mark detection circuits provided in an optical disk device will be described with reference to the drawings.

FIG. 6 shows the structure of the sector described above.

At the beginning of the sector is a sector mark 61 indicating the starting point.

In order, there is a pull-in section 62 for a phase-locked loop (PLL) that generates a clock for demodulating the address information of that sector, an address mark 63 that indicates the starting point of the address area, and an address area 64 in which address information is recorded. , PLL retraction section 62. Address mark 63. The address area 64 is provided repeatedly several times. Furthermore, OD F (Offset) is used to adjust servo systems such as autofocus and autotracking.
Detection Flag) Area 65, Read/
GAP area 6 to absorb light switching time etc.
6. PLL pull-in section 67 for obtaining a clock for demodulating data; data mark 68 indicating the start of data;
There is a data area 69 for recording user data. Of these, the area from sector mark 61 to address area 64 is often preformatted during disk manufacture.

FIG. 7 shows an example of the structure of a sector mark and a reproduced signal of the sector mark (after binarization). Track 7 as shown
1, the reproduced signal consists of a section where it becomes "L" and a section where it becomes "0". For convenience of explanation, the modulation method is (2,
7) Assume that RLL is used. "■" indicating the length of each section in FIG. 7(B) indicates the width of one clock after modulation.

FIG. 8 is a block diagram showing a conventional sector mark detection circuit disclosed in, for example, Japanese Unexamined Patent Publication No. 169337/1983.

In the figure, a reproduction signal reproduced by a reproduction head from an optical disc (not shown) is amplified by an amplifier 81, sent to a binarization circuit 82, and binarized.

The binarized signal (FIG. 7(B)) is determined by the width detection circuit 83 whether it is a sector mark constituent pattern (10T or 6 "l" in this example). This output is input to a detected position storage circuit 84 and parallelized, and the output is sent to a threshold circuit 85. If, for example, three or more of the five detection signals are detected, it is determined that it is a sector mark, and a detection signal is output.

FIG. 9 is a detailed block diagram of the width detection circuit 83 shown in FIG. 8. A clock generator 91 generates a high frequency clock, and a counter 92 counts the generated clocks. At that time, the counter 92 is used only for a period when the binary signal in FIG. 7(B) (the output of the binary circuit 82 in FIG. 8) is 1".
Detect the width by operating . “1” of binary signal
At the end of the process, the contents of the counter 92 are determined by a decoder 93 and a width detection signal is sent out.

FIG. 10 is a detailed block diagram of the detection position storage circuit 84. The detection position storage circuit holds the detection position (timing) of the pattern signal detected by the width detection circuit. IOT
and 6T pattern signals are generated in time series, taken into respective shift registers 1003 and 1004, and taken out in parallel. This parallelized signal is input to the threshold circuit 85. In the threshold circuit 85, m or more of the n width detection signals inputted are pattern signals of IOT.
Or if it is 6T, it outputs a sector mark detection signal, for example n=5. If m=3, RC3+ sc<
+sc@=configured to output 16 combinations of width detection signals.

FIG. 11 is a diagram showing the operating principle of sector mark detection. The sector mark composition pattern is IOT or 6 “1”
” is detected ((1101), (1102)),
Shift register 100 of each detected position storage circuit 84
3. Input to 1004, signal line (1005 in Figure 10)
), (1006), (1007), (100
8) , (1009), Fig. 11 (1105)
, (1106) , (1107) , (110
g) A pulse as shown in (1109) is output. That is, if all "1"s of the JOT and 6T pattern signals constituting the sector mark are detected at accurate positions, (1005), (1006), (1007) in FIG.
), (1008), (1009) signals at the same time”
The circuit is configured so that the signal line becomes "1". At other times, at most one signal line becomes "1".

For example, when three or more pattern detection signals out of five pattern detection signals are generated at a predetermined timing, the threshold circuit 85 outputs a sector mark detection pulse (1110) to 8.
If the mark is configured so that pressure is applied, normal mark detection can be performed even if pressure cannot be detected on two out of five marks due to a defect in the medium or the like.

[Problems to be Solved by the Invention] A condition that the sector mark detection circuit described above should have is that the probability of detection errors and false detections is low.

Causes of detection errors include media defects, noise, disk eccentricity, and motor wow and flutter. Furthermore, since the sector mark is located at the beginning of the sector, a clock synchronized with data by a PLL cannot be used to detect it; in other words, it is necessary to detect it asynchronously.

Therefore, there is essentially a possibility that there is a deviation of ±1 clock when detecting the configuration pattern of the sector mark (in this example, IOT and six "1"s) and storing the detected position. , (Detection of the configuration pattern can be handled by providing the decoder 93 in FIG. 9 with a redundancy of ±1 clock.) FIG. 12 is a diagram explaining such a situation.

In this example, the first IOT pattern is 9T and the trailing edge is missing, so the pattern detection signal is output one clock earlier. The last IOT, on the other hand, has an extended trailing edge and becomes II.
Since it is T, the detection signal is output with a delay of one clock. Furthermore, since the trailing edge of the third 6T is missing, resulting in 5 guns, the detection signal is output one clock earlier. As a result, three or more pattern detection signals input to the threshold circuit 85 do not become 'l' at the same time, and no mark detection signal is output (1210).

In order to prevent this, it is possible to lower the threshold level so that, for example, two or more detections are sufficient, but lowering the threshold level increases the probability of false detection.

In addition, in recent years, such circuits are often integrated into gate arrays together with other circuits, but as the demand for smaller devices increases,
It is also necessary to reduce the circuit scale as much as possible when forming a gate array. For example, if the same channel clock (after 2,71RLL modulation) is supplied to the width detection circuit and detection position g self-memory circuit in FIGS. 9 and 10,
6 in the shift register 1003 using only the detection position storage circuit section.
0 bit, and a 48-bit flip-flop is required in the shift register 1004, resulting in a total scale of about 1000 gates. Furthermore, if a data clock (frequency of U/2 of the channel clock) is supplied to the width detection circuit 83 and the pressure detection position storage circuit 84, the fpIA detection circuit 83
Although the number of flip-flops in the detection position storage circuit 84 is approximately halved, it becomes difficult to provide redundancy to the width detection circuit 83.

In other words, one period of the data clock is T (T'= 2x
), then the sector mark configuration pattern is 5T'
and becomes 37'. Therefore, if this pattern pressure detection is provided with a redundancy of ±1 clock each, it may become impossible to distinguish between 57' and correction, resulting in a drop in detection accuracy.

[Means for Solving the L Problems] In order to solve the above problems, the present invention provides a method of converting a predetermined pattern signal from among reproduced signals reproduced from a recording medium on which a predetermined mark signal is recorded at a first frequency. and means for storing the detected timing of the plurality of pattern signals detected by the upper self-detecting means in synchronization with a clock having a second frequency lower than the first frequency. and means for inputting a plurality of signals from the storage means at a predetermined timing, determining the number of signals, and applying a mark detection signal if the number is equal to or greater than the predetermined number.

The present invention is further characterized in that the input signal from the detected position storage means to the determination means is a pulse having a width greater than one clock width of the second clock.

[Function] The present invention enables a predetermined mark signal to be detected with high accuracy and to reduce the circuit scale with the above-described configuration.

[Example] Hereinafter, one embodiment of the present invention will be briefly described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a sector mark detection circuit according to the present invention.

In the figure, 11 is a width detection circuit, 12 is a pattern detection position storage circuit, 13 is a threshold circuit, 101 is a binarized reproduction signal, 102 is a width detection signal corresponding to the 6-piece pattern, 103 is an IOT 104 to 108 are pattern detection signals, 109 is a sector mark detection signal, and 14 is a clock generator that generates a channel clock 110 and a data clock 111.

A playback signal 101 read from the optical disc by the playback head and binarized by the binarization circuit is sent to the width detection circuit 11.
is input. The width detection circuit 11 is configured as shown in FIG. 2, for example. That is, the input binary signal is (2,7
) RLL modulation modulator channel clock 110
The data is taken into a 3-bit shift register 21. The reason why the channel clock 110 is supplied is to distinguish the patterns constituting the sector mark and to provide detection redundancy of approximately ±1 clock, as described above. In 22, the decoder 22 determines that the width of "1" of the input binary signal is 9T,
], OT, pattern detection signal 10 in case of IIT
2 of the input binary signal, and ``1'' of the input binary signal.
When the width of " is 5T, 6T, or 7 pieces, the pattern detection signal 103 is output.

For example, if the contents of the shift register 21 are 011111111110x 01111111110Xx Outputs the detection signal 103 when 0111110xxxxxx 01111110xxxxxx 011111110xxxx At this time, the detection signal 102 may be set to 8 times.

X may be either “0” or “1”.

Next, the pattern detection signals 102 and 103 are sent to the detection position storage circuit 12. For example, a data clock 111 is supplied to this memory circuit. That is, by supplying a high-frequency channel clock to the width detection circuit 11, which requires accurate pattern detection, and operating the detection position storage circuit 12 with a low-frequency data clock, compared to the case where the width detection circuit 11 is operated using a channel clock. The number of gates in the position detection circuit can be approximately halved. The reason for this will be briefly explained.

When the reproduced signal (b) of the sector mark portion in FIG. 7 is expressed using a data clock, it becomes as shown in FIG. 5(c). In order to delay the pulse at the position Pi to the position P2 and output it to the threshold circuit, flip-flops for the number of clocks between PL and P2 are required. Totally 3 + 3 ÷ 7 ÷ 3 + 3
It is sufficient to have flip-flops for +3+3+5=30 bits. However, if a channel clock is used for this purpose, its period is half that of the data clock, so 60 bits of flip-flops are required.

Therefore, by supplying a data clock to the detected position storage circuit, the number of flip-flops can be halved, and the number of gates when formed into a gate array can also be halved.

The configuration of the detected position storage circuit 12 is as shown in FIG. Unlike the circuit shown in FIG. 10, the signal to the threshold circuit 13 is obtained by ORing the outputs of successive stages of the shift registers 31 and 32 using OR gates 33 to 37 as shown in FIG. output as a pulse. By doing so, it is possible to stably detect a sector mark even if the pressure detection position shifts by about ±1 clock when driving the detection position storage circuit using a slow data clock.

FIGS. 5(a) and 5(b) are diagrams for explaining the timing of the sector mark detection operation in this embodiment. The reproduced binary signal 101 from the binarization circuit is sent to the shift register 21. of the width detection circuit 11. When input to the decoder 22, the 6T and IOT pattern detection signals 102 and 103 are output, and input to the shift registers 32 and 31 of the pattern detection position storage circuit 12. And signals 104-108 are connected to gates 33-3
7, it is converted into 8 pulses with a width of 3 clocks. These signals 104-108 are sent to the threshold circuit 13,
Since three or more of the three or more pattern detection signals are generated simultaneously, the safeter mark detection signal 109 is output.

However, as shown in FIG. 5(b), even if there are 9 or 5 patterns in the reproduced binary signal 101, the signals 104 to 1
Since 08 is pressed with a width of 3 clocks, stable detection is possible even if there is a shift of several clocks due to noise, eccentricity of the disk, etc. Furthermore, by appropriately selecting the pulse width input to the threshold circuit, the sector mark detection signal will not be output at a position other than the original position.

In the above embodiment, for convenience of explanation, it is assumed that (2,7) RLL modulation is performed. Needless to say, by supplying the voltage, it is possible to reduce the circuit scale without reducing the pressure detection accuracy.

[Other Embodiments] In the above embodiments, the threshold circuit processes five inputs from the detection position storage circuit without distinguishing between them. If, for example, three or more of a total of five inputs from the three patterns are detected at a predetermined timing, a mark detection output is generated.Therefore, as shown in FIG. ,
If the IOT pattern shift register and the 6T pattern shift register are shared without distinction, the number of gates can be further reduced. In this case as well, clocks of different frequencies are supplied to the shift register 41 and the shift register 43, although not shown. Note that the signal 401 is the logical sum of the signals 102 and 103 in FIG. 5(a).

[Effects of the Invention] As explained above, according to the present invention, special marks different from normal data such as sector marks can be created with high accuracy without being affected by media defects, eccentricity, noise, motor wow and flutter, etc. It is now possible to measure pressure with a small circuit scale.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a block diagram showing a width detection circuit, FIG. 3 is a block diagram showing a pattern detection position storage circuit, and FIG. 4 is a block diagram showing another embodiment. Block diagram to explain, Fig. 5 (a), (b), (
c) is a timing diagram explaining the sector mark detection operation of the present invention, and FIG.
A diagram showing an example, FIG. 7 A diagram showing an example of an IT sector mark,
FIG. 8 is a block diagram showing a conventional example, FIG. 9 is a block diagram showing a width detection circuit of a conventional example, FIG. 10 is a block diagram showing a pattern pressure position storage circuit of a conventional example, FIG. 1st
FIG. 2 is a timing diagram showing a conventional sector mark detection operation. 11 is a width detection circuit, 12 is a detection position storage circuit, and 13 is a threshold circuit.

Claims (2)

[Claims] (1) means for detecting a predetermined pattern signal from among reproduced signals reproduced from a recording medium on which a predetermined mark signal is recorded, in synchronization with a clock of a first frequency; and a plurality of signals detected by the detection means. means for storing the detected timing of the pattern signal in synchronization with a clock having a second frequency lower than the first frequency; inputting a plurality of signals from the storage means at a predetermined timing and determining the number of the signals; and means for outputting a mark detection signal if the number is greater than or equal to a predetermined number. (2) Mark detection according to claim 1, wherein the input signal from the detected position storage means to the determination means is a pulse having a width greater than one clock width of the second clock. circuit.