JPH0411403A - Signal transmission line - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is configured to be connected to an output terminal or the final stage of signal processing for only the minimum necessary time when reproducing the signal source output of a digital signal. Regarding signal transmission paths.

[Conventional technology]

In a signal transmission line that transmits the output of a signal sound source, such as in audio equipment, the output signal of the signal sound source itself is amplified, and at the same time, all the noise contained in it and the noise generated in the amplification and reproduction system are amplified. . The ratio between the noise level generated by the amplification and reproduction system when there is no signal sound source output and the signal level when the signal sound source is output and amplified and reproduced is called the SN ratio.
This SN ratio is a value that indicates the performance of an audio device, and is influenced by all the wiring inside and outside the device and all the amplification elements inside the device. Furthermore, in digital equipment, signals are converted into analog signals using D/A converters and then amplified and reproduced, but the noise generated during conversion is at a level so large that it affects the S/N ratio of the reproduction system. Therefore, a gate circuit is inserted after the D/A converter, and the gate circuit is normally closed and inactive as a signal transmission path. It has also been proposed to open the gate circuit only when a signal to be amplified arrives.

[Problem to be solved by the invention]

When a signal to be amplified arrives, the internally generated noise is at a lower level than the signal to be amplified, so it often does not pose a problem for the output from the speaker.

On the other hand, when no signal to be amplified has arrived at the input terminal, only noise is constantly amplified, which poses a problem.

Furthermore, the gate circuit control means that have already been proposed have the disadvantage of being complicated when adjusting the timing for opening the gate circuit.

An object of the present invention is to improve the above-mentioned drawbacks, and to cut off the signal transmission path when no signal to be amplified is input.
It is an object of the present invention to provide a signal transmission line that achieves the same effect as that of improving the N ratio.

[Means to solve the problem]

FIG. 1 is a diagram showing the basic configuration of the present invention. In Fig. 1, l is a digital signal source, 2 is a D/A converter that is the next stage of the signal source, 3 is a signal output terminal, 4 is a gate means, and signals are transmitted from signal source 1 to terminal 3. forming a road. 5 indicates signal state detection means.

The present invention has the following configuration in a signal transmission line that outputs a digital signal from a signal source 1 to an analog signal via a D/A conversion means 2 and a signal gate means 4 to a signal output terminal 3. There is.

That is, a signal state in which the state of the signal is detected upon receiving the output signal of the signal source 1 of the digital signal, and a detection signal is generated a predetermined time after the output signal of the signal source 1 of the digital signal reaches a predetermined state. A detecting means 5 is provided, and the gate operation of the signal gating means 4 is controlled by the output of the signal state detecting means 5.

[Effect]

The output of the digital signal source in Fig. 1 is D/
The signal is converted into an analog signal by the A conversion means 2 and reaches the gate means 4. Since the gate means 4 is closed at peak times, the analog signal does not reach the signal output terminal 3 immediately. The output of the digital signal source 1 is applied to a signal state detection means 5 to detect the state of the digital signal. That is, the fact that the digital signal has started to be applied to the detection means, that it continues to be applied, and that the application has ended;
Detect each state. Then, the signal detected as being continuously applied is sent to the gate means 4 to open it. Therefore, the converted analog signal reaches the signal output terminal 3. The signal state detection means 5 sends the next detection signal to the gate means 4 after a predetermined period of time after the application of the digital signal ends and a predetermined state is reached, for example. The gate means 4 is open until that signal, and thereafter the gate means 4 is closed. Therefore, the analog signal reaches the output terminal 3 for a time approximately equal to the time that the digital signal continues to be output from the signal source l.

〔Example〕

In FIG. 2, as an embodiment of the present invention, the signal state detection means 5 is specifically shown surrounded by a dashed line, and the others are shown in blocks. In FIG. 2, 11 is a serial data line, 12 is a serial data line,
is a shift clock line, 13 is a latch clock line, 50 is a shift register, 51 is a latch circuit, 52, 57.58
is an inverter, 53 is a non-zero detector, 54 is an n-stage counter, 55 is a D-type flip-flop, and 56.59 is an AND circuit. Digital data from a digital signal source 1 is sent to a D/A converter 2 and a shift register 50 via a data line 11. The shift clock and latch clock each send a timing clock to a D/A converter or the like through clock lines 12 and 13. Serial data input to the shift register 50 is converted into parallel data, and its operation is controlled by the tarlock of the shift clock line 12. When one predetermined data becomes parallel, it is held in the latch 51.

The holding timing is performed at the rising edge of a signal obtained by inverting the clock of the latch clock line 13 by the inverter 52.

Next, the non-zero detector 53 detects the presence or absence of data in a non-zero state (one of the outputs of the latch 51 is in the "H" state) with respect to the output of the latch 51 for one data. Therefore, a logical operation is performed using an OR gate that performs an OR logical operation on all the outputs of the latch 51. The n-stage counter 54 is cleared when the clear terminal CLR is input at "H".

When "L" is input to the clear terminal CLR and a clock is input to the clock terminal CLK, the count is incremented at the rising edge.

“n” in n stages is latch clock cycle time x 2+n-
11 or the maximum time for all "0" in the serial data (for example, 25 msec when corresponding to a half wave of the lowest value of the generated analog frequency of 20 Hz). The input to the clock terminal CLK is once subjected to a logical operation by an AND circuit 56. In the AND circuit 56, when the output signal Qn of the counter 54 is "L", the inverter 57 inverts the output signal Qn.
After performing a logical operation on the clock of the latch clock line 13, the counter 54 is counted up.

Next, the input to the clear terminal R of the D type flip-flop is “
When it is "H", it is cleared and the input data to the D terminal is latched at the rising edge of the clock CK.

When Qn of the counter 54 is "H", the AND circuit 59 performs an AND logical operation on Qn and the signal obtained by inverting the clock of the latch clock line 13 by the inverter 58, and the rising edge of the signal is input to the data terminal. latches the current Qn (in this case only when it is “H”). The Q of the D-type flip-flop becomes "L" and is applied to the gate circuit 4.

FIG. 3 is an operational waveform diagram of FIG. 2. In Figure 3,
The upper half is the output of the digital signal source I and the latch 5.
The output timing of I and the output timing of the non-zero detector 53 are shown. It can be seen that the data in the latch 51 is delayed by one data when compared with the data on the serial data line 11. The lower half of FIG. 3 macroscopically shows the waveform diagram of the upper half. From when the output of the non-zero detector 53 becomes "L", the counter 54 is counted up by the latch clock. When the count value Qn becomes "H", the "H" output is latched by the D-type flip-flop 55, so that the output Q becomes "L". Thereafter, when the output of the non-zero detector 53 becomes "H", the counter 54 is cleared and the D-type flip-flop 55 is reset, and thereafter the counter 54 does not count up. Further, the output of the D-type flip-flop 55 is either Q or "H".

Next, FIG. 4 is a diagram showing the configuration of the next embodiment.

In FIG. 4, the signal state detection circuit 5' is formed on a common substrate with at least the signal source 1 of the digital signal. In other words, the signal state detection circuit 5 detects the signal source 1 of the digital signal.
This figure shows a case in which it is formed in the same integrated circuit (LSI). Furthermore, since the signal state detection circuit 5' can directly detect the parallel data generated by the digital signal generator 14 without converting it into serial data, the second
A shift register 50 and a latch 51 compared with the embodiment shown in the figure.
I haven't used it. Parallel to Naori/A converter 2 -
After the parallel data is converted into serial data by the serial converter 15, it is sent out via the data line 11. The digital signal generator 14 outputs not only parallel digital data but also various clock signals for converting these data into serial format. In FIG. 4, reference numeral 15 denotes a parallel-to-serial converter q, which converts digital data in parallel format into serial format.

When the signal from the negative edge detector 18 is input to the load terminal LD, the data applied to the converter I5 is taken in and shifted out according to the input clock 5C17 of the clock terminal CLK. SC is inverted by an inverter 19 and output via a shift clock line 12. Negative edge detector 18 detects and generates a falling edge of latch signal LCI6 in order to generate a signal to load terminal LD of parallel-to-serial converter 15.

FIG. 5 is a diagram showing a block configuration in which the time from when the digital signal reaches a predetermined state to when a detection signal for controlling the gate operation is generated can be arbitrarily set. In FIG. 5, 60 is a central processing unit such as a microcomputer;
1 is a data bus, 62 is a data coincidence detection circuit, and 63 is a time data latch. 1.53, 54.58.59
is the same as shown in FIG. FIG. 6 is an operational waveform diagram for FIG. 5. Central processing unit 60 sends time data for starting a gate operation to time data latch 63 via data bus 61 .

The counter 54 is cleared when the clear terminal CLR is "H", and counts up at the rising edge of the terminal CLK to which the latch clock is applied when the clear terminal CLR is "L". Since the output of the non-zero detector 53 is applied to the clear terminal CLR of the counter 54, the counter 54 starts counting up from the time the detector 53 starts sending out the detection signal "L" as shown in FIG. Start. The data coincidence detection circuit 62 converts the data of the time data latch 63 into the counter 54.
When the value of the counter 54 matches the value of the counter 54, the output "H" is sent to the D-type flip-flop 55 as data. The D-type flip-flop 55 is cleared when the output of the non-zero detector 53 is "H", and operates in response to the input signal to the next data terminal or clock terminal CK.

Since data D is taken in at the rising edge of the clock terminal CK, the output of the data coincidence detection circuit 62 is sent to the D terminal, and the latch clock is inverted by the inverter 58 and the clock obtained by performing a logical operation by the AND circuit 59 is sent to the CK terminal. , the output of the data coincidence detection circuit 62 is latched as shown in FIG. Therefore, Q becomes "L". The gate circuit 4 can start gate operation by this signal. The time from the time when the counter 54 starts counting until the time when the data matching detection circuit 62 detects the data can be arbitrarily set using data from the central processing unit 60.

FIG. 7 shows a digital signal source/D/A as another embodiment.
A case is shown in which a plurality of converters are treated as a set, each set is provided with a signal state detection circuit and a gate circuit, and two sets of the set are provided. In comparison with the signal state detection circuits 5 and 5' in FIGS. 2 and 3, the signal state detection circuits 50 and 51 are circuits that detect when signals from a plurality of digital signal sources are all "0"; For example, assume that an OR gate is inserted on the input side. According to this configuration, data signals of a plurality of signal sources can be guided to a smaller number of signal output terminals.

FIG. 8 is a block diagram of an electronic musical instrument as an application example of the present invention. In FIG. 8, the keyboard section 20 is composed of a keyboard including a plurality of keys for controlling musical tone generation, and may be composed of a plurality of m-keyboards. The panel section 21 includes switches for setting the timbre of musical tones, a display device for indicating the status, a tablet switch for selecting the timbre, and the like. The ROM 22 consists of a program and a data section, and controls the operation of the central processing unit 60, and the data is related to various processes. The RAM 23 has an area for temporarily storing data for processing related to the keyboard section 20, the panel section 21, and the signal source 1 of the digital signal. Therefore, the central processing unit 60
is the keyboard section 20 according to the program in the ROM 22.
The key switch included in the key switch is scanned and its status is stored in the RAM 23.
The state of the switch on the panel section 21 is scanned and the state is stored in the RAM 23.

Also, based on the information stored in the RAM 23, the ROM 22
The digital signal source 1 transmits data in accordance with the data so as to cause the digital signal source 1 to generate desired digital data (music waveform data). In addition, a device that controls the gate time (time of the control signal to the gate circuit 4) in the signal state detection circuit 5,
-It will also be sent in the evening.

[Effects of the Invention] In this way, according to the present invention, so-called noise during silent periods is effectively blocked, so that when viewed before and after silent periods, the signal-to-noise ratio after passing through the gate means in the signal transmission path is The ratio is significantly improved compared to the signal-to-noise ratio before the gating means. Therefore, it is effective when applied to public address equipment and audio equipment.

In addition, since it is easy to convert the signal state detection means into a digital circuit, if this configuration is adopted, it can be integrated with the signal source,
A more compact signal transmission path can be obtained. Furthermore, control when arbitrarily setting the operation control time of the gate means can be easily performed.

4 and 5 are diagrams showing the configuration of another embodiment of the present invention, FIG. 6 is an operation waveform diagram of FIG. 5, and FIG. 7 is a diagram showing the configuration of another embodiment of the present invention. FIG. 8 is a diagram showing an example of application of the present invention.

l - Source of digital signal 2-D/A conversion means 3-A language output terminal 4...-gate means 5-a Speech state detection means Patent applicant: Kawai Musical Instruments Manufacturing Co., Ltd. Representative Patent Attorney Eisuke Meiki

[Brief explanation of drawings]

Fig. 1 is a diagram showing the principle configuration of the present invention, Fig. 2 is a diagram showing the configuration of an embodiment of the invention, and Fig. 3 is a diagram showing the configuration of the embodiment of the present invention.
Operation waveform diagram of the figure, Procedural amendment (voluntary) Procedural amendment (voluntary) June 6, 1990 2゜Name of invention Signal transmission line 3, name related to amendment person case (141)

Claims (1)

[Scope of Claims] I. A signal transmission path that outputs the digital signal to a signal output terminal via D/A conversion means for converting the output of a signal source of the digital signal into an analog signal, and a signal gate means, comprising signal state detection means for detecting the state of the signal upon receiving an output signal from the signal source of the digital signal, and generating a detection signal a predetermined time after the output signal of the signal source of the digital signal reaches a predetermined state; A signal transmission line characterized in that the gate operation of the signal gate means is controlled by the output of the signal state detection means. II. The signal transmission line according to claim 1, wherein the signal state detection means is configured to be able to process parallel signals, and at least the signal source of the digital signal is formed on a common substrate. . III. Output to the signal output terminal via D/A conversion means that converts the outputs of the signal sources of the plurality of digital signals into analog signals, and signal gate means whose number is smaller than the number of signal sources of the plurality of digital signals. configuring a signal transmission path, detecting the state of the signal upon receiving the output signal of the signal source of the digital signal, and generating a detection signal a predetermined time after the output signal of the signal source of the digital signal reaches a predetermined state; 1. A signal transmission line comprising a signal state detection means for controlling a gate operation of a corresponding signal gate means by the output of the signal state detection means.