JPH04115367A - Layout pattern designing device for analog lsi function cell - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention [Object of the Invention] (Industrial Application Field) The present invention relates to a layout pattern design device for analog LSI functional cells, and in particular, to an analog basic design device that is used many times in pattern design of LSI chips. The present invention relates to a device for efficiently designing a layout pattern of functional cells.

(Prior Art) Conventionally, in the design of digital LSIs, a method such as the standard cell method in which basic cells are registered in advance and the design is performed using these cells has been generally used. At this time, the symbolic layout method is used when designing cell patterns. In this method, a rough layout of the target circuit is input in advance using symbols of elements and wiring, and an error-free pattern is generated by compaction according to the design rules of the LSI pattern manufacturing process. Therefore, the symbolic layout method changes the element shape according to the manufacturing process without changing the connection state of the circuit.
This can be said to be a method of redesigning basic cells so that the compaction process does not violate design rules.

However, there are the following problems when applying this method to functional cell design of analog LSI.

In the case of analog circuits, there are many changes to the basic layout pattern, and the range of changes in the shape of elements is wide.

Therefore, the size of the symbol and the real pattern are greatly different, and when compaction is performed after real pattern conversion, there is a possibility that the relative positional relationships between elements, between interconnects, or between elements and interconnects may deviate greatly. In the case of analog circuits, these relative positions are likely to have a negative effect on the electrical characteristics of the circuit, and as a result, the layout pattern generated from the basic pattern becomes worthless. This is the first problem.

The second problem is that since the connection state of the circuit is not changed at all, the range of patterns that can be generated from the basic layout pattern is limited.

As described above, simply applying the symbolic layout method conventionally used in digital LSI design to analog circuits does not necessarily result in a satisfactory pattern design.

(Problem to be solved by the invention) As described above, the symbolic layout method conventionally used for functional cell design of digital circuits is difficult to solve when the circuit connection state is partially changed or element values are significantly changed. In some cases, it has not been possible to take measures to prevent the relative positional relationships of elements and wiring from shifting significantly.

The present invention has been made in view of the above, and its purpose is to efficiently reuse the layout pattern of an analog LSI functional cell that has already been designed, and to change the connection state of the circuit or the element value. An object of the present invention is to provide a processing device that can create a layout pattern of analog functional cells having high-quality electrical characteristics in a short time even when the circuit is significantly changed.

[Structure of the Invention] (Means for Solving the Problems) The analog LSI functional cell layout pattern design device of the present invention for achieving the above object includes means for creating a basic circuit diagram, and an analog LSI that has already been designed. means for creating a basic layout pattern corresponding to the basic circuit drawing based on the layout pattern of the functional cell, taking into account the range of characteristics required of the functional cell, and specifying changes to element values of elements in the basic circuit drawing; means for changing an element shape pattern corresponding to the specified element value change; means for incorporating the changed element shape pattern into the basic layout pattern; and a means for resolving a violation of a design rule.

(Function) In the case of analog circuits, there are many changes to the basic layout pattern, and the range of shape changes is wide. Therefore, it is important to create a basic layout pattern that takes these influences into consideration in advance.

In the analog LSI functional cell layout pattern design device of the present invention, first, the circuit configuration and element values to be registered as a cell and the range of change thereof are determined. Next, a basic layout pattern is created that takes into consideration the range of changes in the electrical characteristics of the analog circuit and the element shape. In this way, the present invention takes into account shape change situations that may occur in advance, so even if the cell layout is actually changed (generation of reused patterns), the relative positional relationships of elements and wiring will not change. There is no significant deviation.

After making these preparations, the element whose shape is to be changed and its element values are set. Determine the changed shape and incorporate that shape into the basic layout pattern. Violation of design rules between the changed element and its surrounding layout, and violation of design rules regarding the element whose shape has been changed,
Violations related to connection information are resolved. As a result, the shape of the analog element, which has a wide range of modification, can be easily and flexibly modified, and the range of application of the basic layout pattern can be expanded.

In addition, by setting the range in which design rule violations are resolved through compaction as narrow as possible, it is possible to maintain the relative positional relationships of elements and wiring in the basic layout pattern as much as possible, thereby realizing the layout that the user intended. can.

Comparing the results of the present invention with those of conventional layout methods, the present invention allows many users to create layouts of analog functional cells with high-quality electrical characteristics by simply registering the basic pattern first. It can be done easily in a short time.

(Example) Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the overall configuration of an analog LSI functional cell layout pattern design apparatus according to an embodiment of the present invention. In the figure, a database 7 is a storage means that stores information necessary for analog functional cell design. The data processing device 8 includes a keyboard 10 and a mouse 1.
According to the input direction from 1, various processes in designing the layout pattern of the functional cell are performed using data in the database 7, and a mask/gutter 9 for LSI manufacturing is generated. The keyboard 10 and mouse 11 are operated by a layout designer. Graphic display 1
2 is a display unit that displays the layout results produced by the data processing device 8;

FIG. 2 shows a specific configuration of the database 7 and data processing device 8 in FIG. 1. Element library information storage unit 13, design rule information storage unit 1
4, inter-element connection information storage section 15, circuit drawing information storage section 1
6. Basic layout pattern information storage section 17, element value change result information storage section 18, element shape change result information storage section 1
9. Layout pattern result information storage unit 20, circuit diagram creation processing device 21, basic layout pattern creation processing device 22, element value change processing device 23, element shape change processing device 24, process of incorporating shape change elements into the basic layout pattern Device 25, design rule violation resolution processing device 2
Consisting of 6.

Each storage unit 13, 14.15.16.17, 18°19.
20 constitutes the database 7, and each processing device 21.22
．． 23, 24, 25, and 26 constitute the data processing device 8.

The element library information storage unit 13 is a memory that stores library information of elements used in a circuit diagram to be designed. The circuit diagram creation processing device 21 extracts a predetermined element from the element library information storage unit 13 to create a desired circuit diagram, and stores the creation result in the circuit diagram information storage unit 16. Further, information regarding connection relationships between elements is extracted from the created circuit diagram, and the information is stored in the inter-element connection information storage section 15.

The design rule information storage unit 14 stores information regarding design rules used when creating a basic layout. The basic layout pattern creation processing device 22 uses the element library in the element library information storage unit 13 and the inter-element connection information storage unit 1 based on the design rule stored in the design rule information storage unit 14.
A desired basic layout pattern corresponding to the circuit drawing to be designed is created using the inter-element connection information of No. 5.

The creation results are stored in the basic layout pattern information storage section 17.

The element value change processing device 23 changes a predetermined element value of the circuit drawing stored in the circuit drawing information storage section 16 and stores the result in the element value change result information storage section 18 .

The element shape change processing device 24 performs changes based on the changed element values stored in the element value change result information storage section 18, the basic layout pattern in the basic layout pattern information storage section 17, and the design rules in the design rule information storage section 14. Then, the element shape change result is stored in the element shape change result information storage section 19.

The processing device 25 for incorporating the shape change element into the basic layout pattern stores the basic layout pattern in the basic layout pattern information storage section 17 in design rule information storage based on the element shape change result information in the element shape change result information storage section 19. The layout pattern result information storage section 20 stores the results.

The design rule violation resolution processing device 26 reads out the layout pattern result information from the layout pattern result information storage section 20, and reads out the layout pattern result information from the basic layout pattern information storage section 1.
7, the element shape change result information in the element shape change result information storage part 19, and the inter-element connection information in the inter-element connection information storage part 15, the design rule information in the design rule information storage part 14 is calculated. Based on this, design rule violation resolution is executed, and the result is again stored in the layout pattern result information storage unit 20 as layout pattern result information. This layout pattern result information becomes mask pattern data 9,
displayed on the graphic display 12.

FIG. 3 shows a processing flow of the processing apparatus of the present invention.

First, in step a1, the circuit diagram creation processing device 21
A basic circuit drawing is created.

Next, in step a2, a basic layout pattern is created by the basic layout pattern creation processing device 22. This basic layout pattern is created in consideration of the electrical characteristics of the analog circuit and the range of changes in element shape. In this way, the present invention takes into account shape change situations that may occur in advance. Therefore, even if cell layout and wiring are actually changed, the relative positions of elements and wiring will not change significantly.

Next, in step a3, the circuit diagram creation processing device 21
Changes in element values of the basic circuit diagram created by the user are specified using the keyboard 10 or the mouse 11. Note that, if necessary, element values are changed for each element, the subsequent phases are repeated, and the layout is performed while checking the results of the changes during the process.

Next, in step a4, the shape of the specified element is changed by the element shape change processing device 24.

Next, in step a5, the changed element shape is incorporated into the basic layout pattern using the shape changing element incorporation processing device 25 into the basic layout pattern.

Next, in step a6, the design rule violation that occurs around the changed element is resolved by the design rule violation resolution processing device 26.

If it is determined in step a7 that all necessary element value changes have not been completed, the process returns to step a3,
A series of steps a3 to a6 are repeated until the necessary element value changes are completed.

When it is determined in step a7 that all necessary element value changes have been completed, the process proceeds to step a8, where a layout pattern for the newly created analog functional cell is created.

Next, the operation of the analog LSI functional cell layout pattern design apparatus configured as described above will be explained in FIG.
The process will be explained according to the flowchart shown in FIG. 1 while referring to the layout diagrams of each step shown in ) to (h).

First of all, in step a1, for example, FIG.
) Create a circuit diagram of the functional cell as shown in (). In this example, the element value change range of R6 is set from IKΩ to 4Ω.

Next, in step a2, as shown in FIG. 4(b), the resistor R
6, and considering Ω in the change range IKΩ to 4,
Determine the external shape of the element pattern and the shape of the terminal. Then, using these element layout patterns, a basic layout pattern (element arrangement, wiring between elements) of the functional cell is created. In this creation process, Figure 4 (C)
As shown in , if the resistance R6 is simply expanded in the y direction,
Since the relative positional relationship between the elements located above the resistor R6 will be significantly shifted, in this example, the element area is expanded in the X direction, and the element external shape and terminals are set so that the relative positional relationship is not disrupted. In FIG. 4(b), solid lines indicate the first wiring layer, dotted lines indicate the second wiring layer, and x indicates through holes.

The steps up to this point are the preparations necessary to generate an actual functional cell pattern.

Next, in step a3, as shown in FIGS. 4(d) to (f), the element value of the shape changing element R6 is actually set, and in step a4, the element pattern and internal structure pattern are set accordingly. generate. FIG. 4(d) shows an external shape 100 of an element (resistance) pattern with a variable resistance value range of IKΩ to 4Ω, an element terminal shape 102, and a resistance pattern 104 of IKΩ. If the resistance value change is specified and the resistance value is changed from 2 to Ω, please refer to Figure 4 (e
) Create a pattern as shown.

Further, when changing the resistance value to 2.5Ω, a pattern as shown in FIG. 4(f) is created.

Next, in step a5, these are incorporated into the basic layout pattern.

At this point, there is a design rule violation, so
In step a6, compaction processing is used to solve this problem. That is, as shown in FIG. 4(g),
If the connection wiring 106 between the transistor Q3 and the resistor R6 is separated due to changing the shape of the resistor R6,
Connect this using compaction processing.

In addition, in this step, as shown in Figure 4 (h), it is also possible to limit the scope of application of the compaction process to the minimum so as not to shift the relative positional relationship between elements and wiring in the basic layout pattern as much as possible. It is. That is, the range including the resistor R6 is compacted, the design rule error is corrected, and a wiring pattern within the resistor R6 is created.

Thereafter, if necessary, it is also possible to change the element internal configuration pattern (mainly wiring) and perform compaction processing again in order to prevent wasted space from occurring.

Next, when it is determined in step a7 that all necessary element value changes have been completed, the process proceeds to step a8, where a layout pattern for the newly created analog functional cell is created.

The invention is not limited to the above embodiments. In the above example,
Although the steps have been described in detail by focusing on changing the element value of the resistor R6, it is needless to say that the present invention is not limited to this example. Those skilled in the art can implement various modifications without departing from the technical idea of the present invention.

[Effects of the Invention] As explained above, according to the present invention, the circuit configuration and element values to be registered as a cell and the range of change thereof are first determined, and then the electrical characteristics and element shape of the analog circuit are changed. Since the basic layout pattern is created in consideration of the range, the basic pattern of analog LSI functional cells can be efficiently reused, and a layout pattern with high quality electrical characteristics can be designed in a short time.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a block diagram showing a schematic configuration of an analog LSI functional cell layout pattern design device according to an embodiment of the present invention, and FIG. 2 is a configuration of main parts of the embodiment. FIG. 3 is a flowchart showing the overall processing of the embodiment, and FIGS. 4(a) to h) are diagrams specifically explaining each processing step of the embodiment. . 7... Database, 8... Data processing device, 9.
...Mask pattern, 10...Keyboard, 11...
・Mouse, 12...Graphic display, 13
... Element library information storage section, 14... Design rule information storage section, 15... Inter-element connection information storage section,
16... Circuit drawing information storage section, 17... Basic layout pattern information storage section, 18... Element value change result information storage section, 19... Element shape change result information storage section, 2
0... Layout pattern result information storage unit, 21...
- Circuit diagram creation processing device, 22... Basic layout pattern creation processing device, 23... Element value change processing device, 2
4... Element shape change processing device, 25... Processing device for incorporating the shape change element into the basic layout pattern, 6... Design rule violation resolution processing device

Claims (1)

[Scope of Claims] Means for creating a basic circuit drawing, and corresponding to the basic circuit drawing based on a layout pattern of an already designed analog LSI functional cell, taking into consideration the range of electrical characteristics required for the functional cell. means for creating a basic layout pattern for the elements in the basic circuit drawing; means for specifying a change in the element value of an element in the basic circuit drawing; means for changing an element shape pattern corresponding to the specified change in the element value; A layout pattern design device for an analog LSI functional cell, comprising: means for incorporating a shape pattern into the basic layout pattern; and means for eliminating a design rule violation that occurs around the element shape pattern whose shape has been changed. .