JPH04116152U - BiCMOS device - Google Patents

Abstract

(57) [Summary] [Purpose] BiCMOS with improved latch-up tolerance
Provide the device. [Structure] An n ⁺ buried layer and a p ⁺ buried layer are formed on a p-type silicon substrate 1, an n well and a p well layer are formed on these buried layers, and PMOS,
BiCM with NMOS and bipolar transistors formed
In an OS device, a collector diffusion (n ⁺ ) portion 4' reaching the n ⁺ buried layer is formed in the n-well on the side where the PMOS is formed, of the n-well and p-well that electrically isolate the PMOS and NMOS. .

Description

[Detailed explanation of the idea]

0001

[Industrial application field]

This invention is a latch for IC, LSI, etc. formed by BiCMOS process. BiCMOS device with improved reliability by improving upstand capability Regarding.

0002

[Conventional technology]

A BiCMOS device is a bipolar element and a CMOS element formed on the same substrate using an IC process. FIG. 2 is an enlarged cross-sectional view showing a configuration example of a BiCMOS device. In the figure, reference numeral 1 denotes a p-type silicon substrate, on which an n ⁺ and p ⁺ buried layer 2 is formed, and on this buried layer 2 an epitaxial layer 3 is formed by epitaxial growth. An n-well and a p-well are formed in this epitaxial layer 3 by impurity diffusion. Further, a bipolar transistor, PMOS, and NMOS are formed through a LOCOS (element isolation) process. In the manufacturing process, the epitaxial layer that becomes the well and the element isolation are structurally fabricated for both elements at the same time, and the emitter, base, and collector of the bipolar transistor and the source and drain of the MOS transistor are also common. It is possible to manufacture.

0003

[Problem that the idea aims to solve]

Figure 3 shows the circuit diagram (a), schematic diagram (b), and An equivalent circuit diagram (c) is shown. In these figures, n-channel and p-channel The channel MOS is electrically isolated by the n-well and p-well, and the source A PNPN structure (SCR) is formed by a /drain and a p/n well. ( A, B, C, and D shown in schematic diagram b have a PNPN structure) As a result, for example, if a voltage higher than the power supply voltage is applied to the output terminal (OUTPUT), In this case, the SCR turns on and a large current flows in the direction of arrow E as shown in FIG. Since the resistance of the n-well is relatively large, this n-well generates heat, and in some cases, Therefore, the element will be destroyed. The above n-well heat generation/destruction phenomenon is the latch-up phenomenon. Called.

[0004] The PNPN turns on when a voltage higher than the power supply voltage is applied to the output terminal, and current flows through the resistors R ₁ and R ₂ in the N-well and P-well, biasing the parasitic NPN and PNP transistors in the forward direction. This is caused by an external current that acts as a trigger. Therefore, in order to prevent the latch-up phenomenon, it is necessary to reduce the trigger current or lower the values of R ₁ and R ₂ so that the parasitic NPN does not turn on. Although excessive current due to disturbance cannot be handled within the device, R ₁ and R ₂ can be reduced by increasing the concentration of the p/n well.

The present invention was made in order to solve the above-mentioned problems of the prior art, and it provides a BiCM OS device in which the concentration of the p/n well is increased, R ₁ and R ₂ are reduced, and the latch-up resistance is improved. The purpose is to provide.

[0006]

[Means to solve the problem]

The structure of the present invention to solve the above problems is that an n ⁺ buried layer and a p ⁺ buried layer are formed on a p-type silicon substrate, and an n well and a p well layer are formed on these buried layers. In a BiCMOS device on which PMOS, NMOS, and bipolar transistors are formed, an n ⁺ buried layer is reached in the n-well on the side where PMOS is formed among the n-well and p-well that electrically separate the PMOS and NMOS. It is characterized in that a collector diffusion (n ⁺ ) portion is formed.

[0007]

[Effect]

When an excessive voltage is applied to the output terminal of the NMOS region, the generated current passes through the p-well and reaches the n-well below the PMOS, but the current flows through the n ⁺ layer of the buried layer formed under this n-well. and flows to the drain on the PMOS side.

[0008]

【Example】 FIG. 1 is an enlarged cross-sectional view showing an embodiment of the BiCMOS device of the present invention. figure 2, the same elements as in Figure 2 are given the same reference numerals and duplicate explanations are omitted. The difference between this proposal and the conventional example is that the collector diffusion part 4' is formed in the n-well under the PMOS. This is what we are doing. Note that this collector diffusion part 4' is formed on the same substrate. The mask used when diffusing the collector of an npn bipolar transistor is (by forming a pattern for the diffusion layer 4' on this mask). I can do that.

According to the above configuration, even if a voltage higher than the power supply voltage is applied to the output terminal, the current passes through the collector diffusion part 4' and the n ⁺ layer, which is the buried layer, as shown by the dotted line F, and the current flows through the PMOS. Since it reaches the drain (p ⁺ ) side of the resistor, it is possible to reduce the resistance value of the resistors R1 and R2 present in the n-well and p-well shown in the conventional example. As a result, the PNPN structure (SCR) consisting of the source/drain and p/n well is never turned on. Therefore, it is possible to reduce the latch-up phenomenon that is triggered by an external current that forward biases the NPN and PNP transistors present in the device.

0010

[Effect of the idea]

As explained above in detail with the embodiments, according to the BiCMOS device of the present invention, among the n-well and p-well that electrically separate the PMOS and NMOS, the n-well on the side where the PM OS is formed has an n ⁺ Since the collector diffusion layer (n+ layer) reaching the buried layer is formed, the SCR is less likely to be turned on, and the latch-up resistance can be improved and reliability can be improved.

[Brief explanation of drawings]

FIG. 1 is an enlarged sectional view showing an embodiment of a BiCMOS according to the present invention.

FIG. 2 is an enlarged cross-sectional view showing a conventional BiCMOS.

3(a) is a circuit diagram of the CMOS section of FIG. 2; FIG. (b) A schematic diagram of FIG. 2. (c) is an equivalent circuit diagram of FIG. 2;

[Explanation of symbols]

1 p-type substrate 2 Embedded layer 3 Epitaxial layer 4,4' Collector diffusion section

──────────────────────────────────────────────── ─── Continued from front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location 7342-4M H01L 27/06 321 E

Claims (1)

[Scope of utility model registration request] Claim 1: An n ⁺ buried layer and a p ⁺ buried layer are formed on a p-type silicon substrate, an n well and a p well layer are formed on these buried layers, and a PMO layer is formed on these wells.
Bi formed into S, NMOS, and bipolar transistors
In the CMOS device, a collector diffusion (n ⁺ ) portion reaching the n ⁺ buried layer is formed in the n-well on the side where the PMOS is formed of the n-well and p-well that electrically isolate the PMOS and NMOS. BiCM to be
OS device.