JPH04116744A - Simultaneous write method into plural storage devices - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an auxiliary storage device in an information processing device and a multiple storage device that transfers data that needs to be backed up to another storage device in a duplex system. This relates to a method for simultaneous writing to.

[Conventional technology]

The conventional method for dual-system simultaneous writing of dual memory is as described in Japanese Patent Application Laid-open No. 169244/1983, as a method for backing up data.
The self-system storage device and the other-system storage device of the duplexed system are simultaneously accessed from
It was supposed to terminate the bus cycle.

[Problem to be solved by the invention]

The above conventional technology has no problem if the operating speeds of multiple storage devices that write simultaneously are the same, but if the operating speeds of multiple storage devices that write simultaneously are significantly different, the operation of the slower storage device There has been a problem that the overall operating speed is determined by the speed. The present invention provides a method for simultaneously writing to multiple storage devices without reducing the operating speed, and furthermore,
The object of the present invention is to obtain a method for simultaneously writing to storage devices at different addresses.

[Means to solve the problem]

The above purpose is to provide a method for simultaneous writing to multiple storage devices of an information processing device, which has a high-speed main storage device connected to a CPU bus and an auxiliary storage device connected to a system bus. When a write operation is performed to a specific address area of the storage device, the above address area is identified, and the write operation is simultaneously performed to a preset address corresponding to the address area of the auxiliary storage device, resulting in a high-speed write operation to the main memory device. Upon completion, a completion response signal is returned to the CPU, and the CPU moves on to the next operation, but a bus control circuit is provided that has the function of continuing access to the auxiliary storage device until the write operation to the device is completed. This is achieved by

[Effect]

The information processing device that performs simultaneous writing according to the present invention includes an address identification circuit that identifies a specific address area of a high-speed main memory connected to a CPU bus that performs simultaneous writing, and temporarily stores addresses and data that perform simultaneous writing. an address conversion circuit that performs simultaneous writing corresponding to the address of the main memory device and converts it into an address of an auxiliary memory device connected to the system bus, and a CPU bus cycle and a CPU bus cycle end signal sending circuit that sends out a end signal.
It is equipped with a system bus control device, and when the CPU performs a write operation to a specific address area for simultaneous writing in the main memory, the address identification circuit identifies this and stores the above address and data in the buffer circuit. instruct them to do so. The buffer circuit stores the above address and data, and the address stored in the buffer circuit is converted by an address conversion circuit into an address of an auxiliary storage device corresponding to the above address set in advance, and the address is stored in the buffer circuit. Data is written to secondary storage by the system bus control circuit. On the other hand, the CPU bus cycle end signal sending circuit immediately sends the CPU bus cycle end signal when the address area is not a simultaneous write address area for access from the CPU, or even if the address area is a simultaneous write address area, if the buffer circuit is not in use. If the buffer circuit is in use in the simultaneous write address area, the CPU bus cycle end signal is sent when the write operation to the auxiliary storage device on the system bus is completed and the buffer circuit is no longer used. do. In this case, a bus cycle delay occurs. When the CPU receives both the CPU bus cycle end signal from the system bus control device and the CPU bus cycle end signal from the main storage device, the CPU ends the bus cycle.
As long as the buffer circuit is not in use, the PU can complete the bus cycle when the operation of the main memory device ends, and there is no delay in the bus cycle due to simultaneous writing, and the PU can operate at high speed. Furthermore, by making the buffer circuit a first-in, first-out type temporary storage device with an appropriate capacity, the probability that the buffer circuit is in use and the CPU bus cycle is delayed is reduced.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the method of simultaneously writing to multiple storage devices according to the present invention, FIG. 2 is a diagram showing address allocation in the above embodiment, and FIG. 3 is an example of application of the above embodiment. FIG. In FIG. 1, 1 is a CPU, 2 is a main storage device, 3 is a system bus control device, 4 is an address identification circuit, 5 is a buffer circuit, 6 is an address conversion circuit, 7 is a system bus connection circuit, and 8 is a control circuit. , 9 is an auxiliary storage device, 10 is an input/output device control device, 11 is a CPU bus, 12
is the system bus, 13 is the internal bus cycle end signal, 1
4 is an external bus cycle end signal, and 15 is a system bus cycle end signal. In addition, in Figure 2, 16
17 is an address area of the main memory 2 that does not write to the auxiliary memory 9 simultaneously, 17 is an address area of the main memory 2 that does not write to the auxiliary memory 9 at the same time, and 18 indicates an address area that does not write to the auxiliary memory 9 at the same time. 19 is an address area of the auxiliary storage device 9 that is not a target of simultaneous writing, and 20 is an address area of the input/output device control device.

In addition, the address area shown in 16.17 above is the address area of the device connected to the CPU bus 11, and 18.19
．． The address area shown at 20 can be rephrased as the address area of devices connected to the system bus 12.

Next, the operation of the above embodiment will be explained. The address identification circuit 4 includes an address area for simultaneous writing on the CPU bus shown in FIG. Set the address area in advance. The setting method may be set using hardware, or registers may be set using software when starting up the system. The address conversion circuit 6 is preset with a table that converts the address of the simultaneous write target address area of the main memory shown at 16 in FIG. 2 into the address of the simultaneous write target address area of the auxiliary storage shown at 18. put. The setting method may be set by hardware, or by providing registers and setting by software at system start-up.

A case where the CPUI performs a write operation in the simultaneous write address area 16 will be described. Data is written to the main storage device 2 via the CPU bus 11 through the above operations. Further, the address resulting from the above operation is identified by the address identification circuit 4 as being a simultaneous write address area, and the control circuit 8 is notified. The above control circuit 8
returns the external bus cycle end signal 14 to the CPUI,
on the other hand.

When the write operation is completed, the main memory device 2 returns an internal bus cycle end signal 13 to the CPU 1k. Above C
When the PUI receives the bus cycle end signals 14 and 13, it ends the CPU bus cycle of the above operation and moves on to the next operation. Furthermore, before sending the external bus cycle end signal 14 back to the CPUI, the control circuit 8 sets a flag indicating that the system bus control device 3 is in use, and the buffer circuit 5
Then, the address and data outputted to the CPU bus 11 by the above operation are instructed to be stored at - time, the system bus connection circuit 7 is connected to the system bus, and
Instructs to connect to address conversion circuit 6. The address conversion circuit 6 converts the address temporarily stored in the buffer circuit 5 into an address in the address area 18 on the system bus 12 using a preset address conversion table, sends it to the system bus connection circuit 7, and sends the address to the buffer circuit 5. The data temporarily stored in 5 is sent as is to the system bus connection circuit. The system bus connection circuit 7 sends the address and data to the system bus 12.

A write operation is performed on the auxiliary storage device 9. Auxiliary memory bag @9
When the write operation is completed, the system bus end signal 15
is returned to the control circuit 8, and the control circuit 8 instructs the system bus connection circuit 7 to end the system bus cycle, disconnects the system bus connection circuit 7 from the system bus 12, and ends the write operation to the auxiliary storage device 9. . Further, the control circuit 8 resets the in-use flag of the system bus control device 3 and prepares for the next access. In the above example,
When write operations occur consecutively in the simultaneous write address area 16, the next write operation is performed until the write operation to the auxiliary storage device 9 is completed and the system bus control device 3 in use flag of the control circuit 8 is reset. Since the operation is delayed, the CPU bus 11 is put on hold during this time, resulting in a problem that the effects of the present invention are reduced. In order to solve the above problem, the buffer circuit 5 may be a first-in, first-out type temporary storage device and configured to accept a plurality of consecutive write operations. At the time of read access to the simultaneous write address area 16 from the CPUI, the control circuit 8 immediately outputs the external bus cycle end signal 14C.
The access from the CPU 1 is terminated by the internal bus cycle end signal 13 from the main storage device 2.

Next, a case where the CPU performs write or read access to the non-simultaneous write address area 17 on the CPU bus 11 will be described. When an access to the address area 17 occurs, the address identification circuit 4 identifies this and notifies the control circuit 8 of the access. The control circuit 8 immediately sends an external bus cycle end signal 14 to the CPU 1. As a result, when the CPtJ1 receives the internal bus cycle end signal 13 from the main memory, it ends this access.

Next, the CPU moves to address area 1 on the system bus 12.
A case where write or read access to 9 or 20 is performed will be explained. When an access occurs to the address area 19 or 20, the address identification circuit 4 identifies this and notifies the control circuit 8 of the access. The control circuit 8 immediately sends an internal bus cycle end signal 13 to the CPUI, and connects the system bus connection circuit 7 to the CPU bus 11 and the system bus 1.
2 and accesses the auxiliary storage device 9 or the input/output device control device 10 via the system bus 12. When the auxiliary storage device 9 or the input/output device 10 completes a write or read operation, it sends a system bus cycle end signal 15 to the control circuit 8. The control circuit 8 receives the signal and sends the external bus cycle end signal 14 to C.
Return to PU1. The CPUI thus ends the access.

According to the above embodiment, even if a write operation is performed simultaneously to a high-speed main memory device and a low-speed auxiliary memory device, there is an effect that the CPU bus hold time does not increase and the CPU operating speed does not decrease. .

Next, an application example of the above embodiment is shown in FIG.
This will be explained using FIG. In FIG. 3 showing the configuration of this application example, 17a is the 0-system CPTJ system, 17b
is 1 system CPU system, 1a and 1b are CPUs, 2a
and 2b are main storage devices, 3a and 3b are system bus control devices, 9a and 9b are auxiliary storage devices, 10a and 10b are input/output device control devices, lla and llb
is the CPU bus, 12a and 12b are the system buses, 1
6a and 16b are bus connection devices, and 21 is a confounding bus. This application example is a case where the system shown in the above embodiment is duplicated, and one system operates as an active system and the other system operates as a standby system. The above-mentioned spare system operates in a standby state with 1 normal CPU 1a or 1b and main memory bag [2a or 2b, and system bus 12a or 1b].
2b is not used. Bus connection devices 16a, 16b
is a device that connects the system buses 12a and 12b of both systems.

It can be connected or disconnected as necessary. If 17a is the active system and 17b is the backup system, the CP
A standby auxiliary storage device 9b or input/output device control device 10b is connected from U1a through the bus connection devices 16a and 16b.
can be accessed. In the above configuration, when the active system CPU 1a makes a write access to the simultaneous write address area 16 shown in FIG. Writing can be performed to the auxiliary storage device 9b of the system through the bus connection devices 16a, 16b.

As described above, according to this application example, the high-speed main memory, active auxiliary storage, and standby auxiliary storage are
without reducing the operating speed.

This has the effect of being able to write data at the same time.
Since it is possible to simultaneously write to the auxiliary storage device of the standby system, there is an effect that when switching between the active system and the standby system, data from the old active system can be taken over.

〔Effect of the invention〕

As described above, the method of simultaneously writing to multiple storage devices according to the present invention is used in an information processing device having a high-speed main storage device connected to a CPU bus and an auxiliary storage device connected to a system bus. In the method for simultaneous writing to multiple storage devices, when the CPU performs a write operation to a specific address area of the main storage device, it identifies the address area and simultaneously writes data to a preset address corresponding to the address area of the auxiliary storage device. A write operation is performed, and when the write operation to the high-speed main memory device is completed, a completion response signal is sent back to the CPU, and the CPtJ moves on to the next operation. By providing a bus control circuit with a function that continues until completion, data can be written to low-speed auxiliary storage at the same time as high-speed main storage without reducing CPU processing speed, making data backup possible. and C
This has the effect of allowing the PU to operate at high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the method of simultaneously writing to multiple storage devices according to the present invention, FIG. 2 is a diagram showing address allocation in the above embodiment, and FIG. 3 is an example of application of the above embodiment. FIG. 1...CPU 2...Main storage device 3...
- System bus control device 4...Address identification circuit 9...Auxiliary storage device 12
・System bus 13 Internal bus cycle end signal 14・External bus cycle end signal 19.20 ・Address area

Claims (1)

[Claims] 1. A high-speed main memory connected to a CPU bus;
an auxiliary storage device connected to the system bus;
In a method for simultaneously writing to multiple storage devices used in an information processing device, when the CPU performs a write operation to a specific address area of the main storage device, the CPU identifies the address area and writes data to a preset address area corresponding to the address area of the auxiliary storage device. When the high-speed write operation to the main memory is completed, a completion response signal is sent back to the CPU, and the CPU moves on to the next operation, but access to the auxiliary memory is limited to the above-mentioned device. 1. A method for simultaneously writing to multiple storage devices, characterized in that a bus control circuit is provided that has a function of continuing until a write operation to the storage devices is completed. 2. The bus control circuit is provided with a first-in, first-out type temporary storage circuit for temporarily storing the address and data when write operations continue in a specific address area of the main memory device. A method for simultaneously writing to multiple storage devices as set forth in claim 1.