JPH04117526A - Microprogram controller - Google Patents

Abstract

PURPOSE:To deteriorate only the branching performance in the direction where the total processing performance is less affected and to reduce the deterioration of the total processing speed. CONSTITUTION:The muP language of an address designated in an NA field included in the present muP language is regarded as the muP language to be executed next and read out to a read register 5. When the muP language is sent to a repeating register 6 from the the register 5, a branching condition deciding circuit 3 decides whether the muP language is identical with a correct branching destination corresponding to the value of a register CARRY or not. Then the circuit 3 compares the signal of the lowest rank bit of an address register which is delayed by cycle with the selected branching conditions. Thus the correctness of the branching conditions can be judged.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microprogram control device, and more particularly to a microprogram control device with a conditional branching method for microprograms.

[Conventional technology]

Next, a conventional microprogram control device (hereinafter referred to as μP control device °') will be explained.

FIG. 3 is a block diagram showing an example of the configuration of a conventional μP control device that performs conditional branching of a microprogram by simultaneously reading multiple μP words, selecting and executing one of them according to branch conditions. show.

The .mu.P control device shown in FIG. 3 performs conditional branching in two directions, and for this purpose the control memory 2 is constructed to read out two .mu.P words at a time. The output of the address register 1, excluding the least significant one bit, is given to the control storage section 2. Therefore, μP words at even addresses and μP words at odd addresses are read out from the control storage unit 2 at the same time. These two μP words read from the control storage section 2 are input to the selection circuit 4. The selection circuit 4 selects one word from the two words according to instructions from the branch condition determination circuit 3 and supplies it to the read register 5 as the μP word to be executed next, and also selects one word from the two words and supplies it to the read register 5 as the μP word to be executed next. The address of the word is supplied to address register 1.

μP not read to read register 5! ! As shown in FIG. 4, there is an SQ field that controls the execution order of μP, a CTL field that controls controlled devices such as arithmetic circuits, and an NA that specifies the address of the next μP word to be executed.
It consists of a field.

As described above, the value of the NA field is set in address register 1 at the same time as the μP word is read out to the read register, in preparation for reading the next μP word.

The CTL field is stored in each part of the arithmetic circuit 8 in FIG. 3, such as register AR, BR-DR-CARRY (carry).
and controls the adder circuit, etc.

Here, AR-BR is an input register of the adder circuit, DR is a register that stores the addition result by the adder circuit, and CARR is
Y is a register that stores the digit error of the adder circuit.

The ISQ field controls each part of the present μP control device, and mainly controls the execution order of μP by controlling the branch condition determination circuit 3. This operation will be explained using FIG. 5(b). However, it is assumed that there is no relay register 10 shown by a broken line in FIG. FIG. 5(b) is a flowchart showing the execution flow of the microprogram,
One frame represents one μP word. The address of the μP word is shown at the top left of each part, and each μP word is executed from top to bottom according to the arrow.

The upper part of each part is divided into upper and lower parts, and the ISQ field and NA
For example, °'Br in the upper row of the μP word at address A.
``anch to B'' indicates an unconditional branch and indicates that the next μP word to be executed is the μP word at address B. For this purpose, the branch condition determination circuit 3 contains the information that is simultaneously read out from the control circuit 2. The μ whose address is B among the two μP words
The selection circuit 4 is instructed to select the P word. "'DR←AR+BR" and "CARRY -C" in the lower row control the arithmetic circuit 8, add the contents of registers AR and BH, put the result in register DR, and store the digit error at that time in register CARRY. "ConditionalBra" in the upper row of the μP word at address B, indicating that the
nch to C" and Te5t CARRY" indicate conditional branching, and indicate that the μP word at the address in which the least significant bit of address C is replaced with the output of CARRY is the μP word to be executed next. For this purpose, the branch condition determination circuit 3 uses the μP word at address C and the μP word at address C+1 read out simultaneously from the control circuit 2 according to the value of the register CARRY.
The selection circuit 4 is instructed to select one of the words.

That is, when the value of register CARRY is 0, the μP word at address C is selected, and when the value of register CARRY is 1, the μP word at address C+1 is selected. There are many other registers such as register CARRY that are referenced when performing a conditional branch. “Te5t
XXX (“Test for example register CARRY”) indicates the selection of this register to refer to and is indicated in the ISQ field.

[Problem to be solved by the invention]

The conventional μP control device described above has the following drawbacks.

The machine cycles of recent information processing devices have become extremely fast. In such an information processing device, the third
When trying to use a μP control device like the one shown in the figure, the capacity of the control device is becoming larger, and the output of a register such as register CARRY, which is referenced during a μP conditional branch, is passed through a branch condition judgment circuit. , multiple μ
A situation may arise in which the delay time from selecting one of the P words and reading it to the register does not fit within one machine cycle.

For this purpose, a relay register 6 as shown by the broken line in Fig. 3 is used.
is required. Then, since the determination of the information referenced by the conditional branch is delayed by one machine cycle, as shown in Figure 5 (C), after issuing the command to set the condition register (°"CARRY of address A→C'°), , conditional branch instruction (Conditional Branch at address C)
h to D'' and Te5t CARRY'') must be delayed by one step. Therefore, there was a drawback that the overall processing speed became slow.

[Means to solve the problem]

A microprogram (μP) control device of the present invention includes a control storage section configured to read a plurality of μP words at the same time, and a plurality of buffer registers that hold the plurality of μP words read from the control storage section. , a read register that holds the μP word to be executed among the multiple μP words read from the control storage, and which one of the multiple μP Xi read from the control storage in the case of a conditional branch. and a branch condition determination circuit that determines whether to execute the
If the current μP word read out to the read register instructs an unconditional branch, the next μP word specified by the address register is selected from among the multiple μP words read out from the control storage section. Executes reading from the read register as a μP word to be executed at the current μP word, and if the current μP word instructs a conditional branch, predicts the μP word specified by the address register from among the multiple μP words as the branch destination. If the prediction is determined to be correct by the branch condition determination circuit, the predicted μP word is executed as it is; on the other hand, if the prediction is determined to be incorrect, transfers this predicted μP word to multiple μPs held in the buffer register.
In addition to executing one of the words, a μP word specified by the branch judgment circuit in response to a branch condition is selected from among a plurality of μP words held in the buffer register as the next μP word to be executed. It is configured by executing a read to the read register.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

The relay register 6 of the register CARRY shown by a broken line in FIG. 3 is provided corresponding to the read register 5 in FIG. The reason why the relay register is necessary is that the delay time cannot be accommodated within one machine cycle due to the distance between the μP control device and the arithmetic circuit that is the controlled device. Since the flowchart shown in FIG. 5(b) does not change even if the relay register is provided on the read register side as shown in FIG. do.

In FIG. 1, buffer registers 71 to 74 each store four μP words read simultaneously from control storage section 2. In FIG. The buffer register 71 contains μP words with addresses that are multiples of 4, and the buffer register 72 contains μP words with addresses that are multiples of 4 + 1.
The μP word at the address of is stored in the buffer register 73, and the μP word at the address of a multiple of 4 + 2 is stored in the buffer register 74.
The μP word at the address of multiple of 4+3 is stored in .

When the current μP word read into the read register 5 instructs an unconditional branch, the μP word at the address specified by the NA field in the current μP word, as explained in FIG.
The P word is read out to the read register 5 via the selection circuit 41 in the next cycle as the μP word to be executed next, and is executed by the arithmetic circuit 8 via the selection port Fl@42 and the relay register 6.

When the current μP word indicates a conditional branch that refers to the register CARRY, first, as with the unconditional branch described above, the μ of the address specified by the NA field in the current μP word is
The P word is regarded as μp BB to be executed next and is read into the read register 5. And this μP word is read register 5
When the μP word is sent to the relay register 6, the condition determining circuit 3 determines whether this μP word is the correct branch destination corresponding to the value of the register CARRY.

The branch condition determination circuit 3 determines whether this condition is correct or not by comparing the one-cycle delayed signal of the least significant bit of the address register with the selected branch condition (in this case, the value of the register CARRY). If this comparison matches, it is correct.”
′, and if it does not match, it is incorrect.If it is “correct”, the operation is the same as in the case of the elementary conditional branch described above.

The time chart in Figure 2 (a) shows this operation, and this is a case in which the prediction of the conditional branch of the μP word at address B in the flow chart in Figure 5 (a) is successful. In the chart, addresses A, B, C.
The μP word of ... is the address register read register 5.
The data is transferred and executed in the order of relay register 6. When the μP word at address A in relay register 6 is executed, there is no digit shift in the adder circuit, so CARRY is set to “” in the next cycle.
0'' is set.Next, when the μP word at address B in relay register 6 is executed, a one-cycle delayed signal of the least significant bit of address register 1 (in this case, the least significant bit of address C and its The value is O°°) and CARRY
If they match, the conditional branch is determined to be "correct", and in the next cycle, the μP word of address C read out in the readout register 5 is set in the relay register 6, and the readout The μP word at address E is read into the register. In this way, the μP words are supplied to the relay register and executed in the order shown in the flowchart of FIG. 5(a) (case where prediction is successful).

On the other hand, if the branch condition determination circuit 3 determines that the branch is an error, the erroneous μP word in the read register 5 is replaced by the μP word held in the buffer register 73 by the selection circuit 42 and relayed. A selection circuit 41 selects a μP word on the opposite side of the predicted branch destination to be transferred to the register 6 and held in the buffer register 71 or 72 at the same time.
For example, when the predicted branch destination is an even address and the least significant bit of the address register is "O"), the buffer register 72 is read out to the read register 5 by
The μP word in the buffer register 71 is the μP word on the opposite side of the prediction, and when the predicted branch destination is an odd number (when the least significant bit of the address register is 1''), the μP word in the buffer register 71 is the μP word on the opposite side of the prediction. In this embodiment, the branch destination (prediction light) address of the conditional branch is a multiple of 4 + 1, and μPh1 (μP story in the buffer register 73) at the address of multiple of 4 + 2 is as described above. The number of μP words that are read out simultaneously by the control storage unit 2 in FIG. 1 compared to the one in FIG. This is why there are so many.

The above operation is shown in the time chart of FIG. 2(b), which is a case in which prediction of the conditional branch of the μP word at address B in the flowchart of FIG. 5(a) fails. In the same time chart, CARRY is “1”.
” is set in the relay register until the μP word at address B is set to the relay register. The conditional branch is determined to be "'erroneous".Then, in the next cycle, the μP word (C+
1) is set in the read register 5, and the μP word (C+2) in the buffer register 73 is set in the relay register 6. Furthermore, in the next cycle, the μP word (C+2) in the relay register 6 is executed, and the μPI (C+1) previously set in the read register 5 is set in the relay register 6. In this way, Figure 5(a)
The μP words are supplied to the relay register 6 in the order shown in the flowchart (case where prediction fails) and are executed.

As will be explained below, in FIG. 5(a), address C
is the predicted address of the conditional branch instruction issued by the μP word at address B, and is the branch condition register CARR.
If the value of Y is ``0°'', these are the addresses that are executed as a prediction success.Addresses C+2 and C+1 are the addresses that are executed when the prediction fails because the value of the register CARRY is 1''. be.

Comparing FIGS. 5(a) and 5(c), it is clear that the time required from setting the branch condition (CARRY) to referencing it and branching is shorter in FIG. 5<a).

〔Effect of the invention〕

As explained above, the present invention incorporates a prediction method into conditional branching in a microprogram.
As shown in figure (c), the total processing performance can be improved without reducing the performance of conditional branching (the time from setting the branching condition to referring to it and branching) for all branching directions of conditional branching. By reducing only the branching performance in directions that are less affected, it is possible to provide a μP control device with less reduction in overall processing speed.

[Brief explanation of drawings]

Figure 3 shows the time chart for when μ is calculated using the conventional technology.
A block diagram showing an example of the configuration of the P control device, FIG. 4 is the format of the μP word of the μP control device of FIGS. 1 and 3, and FIG. 5(a) is a microprogram of the μP control device of this embodiment. FIGS. 5(b) and 5(c) are examples of flowcharts of the microprogram of the μP control device shown in FIG. 1...Address register, 2...Control storage section, 3.
... Branch condition determination circuit, 4, 41, 42... Selection circuit, 5... Read register, 6... Relay register, 7
・71 to 74...Buffer register, 8...Arithmetic circuit.

Claims (1)

[Claims] Multiple microprogram words (hereinafter referred to as “μP words”)
a control storage section configured to be able to simultaneously read out a plurality of .mu.P words; a plurality of buffer registers that hold a plurality of .mu.P words read from the control storage section; a read register that holds a μP word to be executed, and a branch condition determination circuit that determines which μP word to execute among the plurality of μP words read from the control storage unit in the case of a conditional branch; If the current μP word read into the read register indicates an unconditional branch, the multiple μP words read from the control storage
The μP word specified by the address register from among the P words is read from the read register as the μP word to be executed next, and if the current μP word instructs a conditional branch, the μP words of the plurality of μP words are The μP word specified by the address register is read into the read register as a predicted μP word as a branch destination, and if the branch condition determination circuit determines that the prediction is correct, the predicted μP word is read as is. If it is determined that the prediction is incorrect, execute one of the plurality of μP words held in the buffer register and execute the predicted μP word next. A μP specified by a branch judgment circuit in response to a branch condition from among a plurality of μP words held in the buffer register as a μP word.
A microprogram control device characterized in that it reads a word into a read register and executes it.