JPH04117566A - Logic circuit verifying system - Google Patents

Abstract

PURPOSE:To shorten the time necessary for the design and the verification of a large scale logic circuit by attaining the verification of the logical justice of instruction specification and the verification of the justice of test diagnosis precedure described information and the logical justice of functional specification with a simulation means. CONSTITUTION:A simulation means 4 simulates the action of instruction specification executed by an objective logic circuit by inputting simulation model information (d) prepared by an instruction specification input means 1 and simulates the functional constitution of the objective logic circuit and a logical action by inputting the simulation model information (d) prepared by a functional specification input means 3. Moreover, the test and the diagnosis of the objective logic circuit are executed at hardware designing by using the simulation model information (d) prepared by a test diagnosis procedure input means 2 at simulating. Thus, time necessary for the design and the verification of a large scale logic circuit is shortened and medium resources necessary for it is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic circuit verification method, and particularly to a logic circuit verification method for large-scale logic circuits.

[Conventional technology]

Traditionally, the conventional logic circuit verification method for hardware design of large-scale logic circuits first clarifies the hardware functions of the target logic circuit, and then specifies the instructions to be executed in the target logic circuit in order to evaluate the performance. The validity of the expressed instruction specifications is manually verified, and then a test diagnostic program is created from the instruction specifications to test and diagnose the target logic circuit, and a simulator specific to the target logic circuit is used to run the test diagnostic program. Then, based on the instruction specifications, create a functional specification that expresses the functional configuration and operation of the target logic circuit, and use a logic simulator to verify the logical validity of the functional specification. Was.

Related literature is shown below.

(1) Author Kenji Kani and 2 others, Fundamentals of VLSI CAD, Chapter 1 "Design flow and CADJ" and Chapter 4 "Logic circuit CADJ, Ohmsha (1 (2) Author Hiroshi Inose, Computer system High Reliability, Chapter 7 "Failure Diagnosis", Information Processing Society of Japan (1977) (3) Translated by Shunji Okuyoshi and one other person, Logical Design of Computers,
Chapter 4 "Computer Design", Kyoritsu Shuppan (1983) [Problem to be solved by the invention] The conventional logic circuit verification method described above first clarifies the hardware function of the target logic circuit, and then evaluates the performance. For this purpose, we manually verify the validity of an instruction specification that expresses the specifications of instructions to be executed in the target logic circuit, and then create a test diagnosis program from the instruction specification to test and diagnose the target logic circuit. , verify the validity of the test diagnostic program using a simulator specific to the target logic circuit, and further create a functional specification that expresses the functional configuration and operation of the target logic circuit based on the instruction specifications, and Since the logical validity of the functional specifications was verified using a simulator, there were problems in that a large amount of time was spent designing and verifying a large-scale logic circuit, and a large amount of media resources were required.

SUMMARY OF THE INVENTION An object of the present invention is to provide a logic circuit verification method that can shorten the time required for designing and verifying large-scale logic circuits and requires fewer media resources for this purpose.

[Means to solve the problem]

The logic circuit verification method of the present invention is a logic circuit verification method for hardware design of large-scale logic circuits. (B) simulation model information in a format that allows simulation by inputting test diagnosis procedure description information created for testing and diagnosing the target logic circuit; (C) Functional specification input means for inputting functional specification description information expressing the function of the target logic circuit to create simulation model information in a format that can be simulated; (D ) A simulation means for inputting the simulation model information and performing a simulation.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

The logic circuit verification method shown in FIG.
, a test diagnosis procedure input means 2, a functional specification input means 3, and a simulation means 4.

Then, the instruction specification input means 1 inputs instruction specification description information a that describes the specifications of instructions to be executed in the target logic circuit, and converts it into simulation model information d in a format that can be input to the simulation means 4. Convert.

The test diagnosis procedure input means 2 describes a test procedure and a diagnosis procedure, for example, a test diagnosis program, for testing and diagnosing the target logic circuit, based on the instruction specification description information a whose logical validity is guaranteed. The test diagnosis procedure description information (d) is input and converted into simulation model information (d) in a format that can be input to the simulation means 4.

The functional specification input means 3 generates functional specification description information that describes the functional configuration and logical operation of the target logic circuit in which the target logic circuit is embodied, based on the instruction specification description information a whose logical validity is guaranteed. C is input and converted into simulation model information d in a format that can be input to the simulation means 4.

By inputting the simulation model information d created by the instruction specification input means 1, the simulation means 4 can simulate the operation of the instruction specification executed in the target logic circuit, and also simulate the operation of the instruction specification executed by the functional specification input means 3. By inputting the model information d, the functional configuration and logical operation of the target logic circuit can be simulated, and furthermore, by using the simulation model information d created by the test diagnosis procedure input means 2 during simulation, the target logic circuit can be tested. and diagnosis at the time of hardware design.

Next, the operation will be explained.

FIG. 2 is a diagram showing a concrete image of the logic circuit verification method shown in FIG. 1.

The instruction specification 5 expresses the specification of the instruction executed by the target logic circuit, and describes the instruction word format and the method of expressing the instruction word. el is an image diagram of the instruction format, where the instruction word consists of the operation part OP of the instruction consisting of 4 bits, the first address part R1 of the instruction consisting of 6 bits, and the second address of the instruction consisting of 6 bits. It is expressed that it is composed of part R2. e2 is an image diagram of how to express the command word, and r
rADDJ of ADD△A, BJ represents an addition instruction which is a type of operation part OP of the instruction, rAJ represents the specific address of the first address part R1 of the instruction, and "B" represents the second address of the instruction. Expresses the specific address of part R2, and "," indicates the first address part R1
and represents the second address part R2 delimiter, and rADD as a whole.
ΔA and BJ represent an instruction to "add the value of register A and the value of register B, and store the operation result in register A."

The instruction specification description information a is expressed in a description that can be input by the instruction specification input means 1 based on the instruction specification 5,
rADD: A=A+BJ is the symbol ADD of the addition instruction, and the operation of the addition instruction, that is, "adds the value of register A and the value of register B, and stores the operation result in register A."
It expresses the specification of the command.

The test diagnosis procedure description information (a) expresses the test procedure and diagnosis procedure for testing and diagnosing the target logic circuit based on the instruction specification 5 and the instruction specification description information a. fl represents the test environment setting, which is the first step in the test procedure, that is, the test data setting, and rA=1. B=2J represents setting register A to "1" and setting register B to "2". fQ represents the test command execution, which is the second step in the test procedure, and “ADD△A,
BJ represents that the instruction to be tested is an addition instruction and that an addition operation between register A and register B is to be executed. f3 is the third stage in the test procedure, result verification;
In other words, it expresses comparing the execution result of the test command with the correct value, and rA=3? J represents comparing the value of register A in which the execution result of the test instruction is stored with the correct value "3". f41 f5 represents the fourth step in the test procedure, the result comparison display, and f
4 r OK! J indicates that the execution result of the test instruction and the correct value match, that is, the instruction to be tested was executed normally, and f5 "Error" indicates that the execution result of the test instruction and the correct value match. It expresses that there was a mismatch, that is, the execution of the test target instruction was abnormal.

The functional specification description information C expresses the functional configuration and logical operation of the target logic circuit that embodies the target logic circuit based on the instruction specification 5 and the command specification description information a. gl represents the configuration and logical operation of register A, g2 represents the configuration and logical operation of register B, g3 represents the configuration and logical operation of the adder, and h and ~h5 represent the connections of the logic circuits, respectively. expressing.

First, in order to clarify the hardware functions and evaluate the performance of the target logic circuit, the instruction specification 5, which is the specification of the instruction to be executed in the target logic circuit, is input to the instruction specification input means 1 as instruction specification description information a. The information is input and converted into simulation model information d in a format that can be input to the simulation means 4. Then, by inputting the simulation model information d outputted by the instruction specification input means 1 to the simulation means 4, the operation of the instruction specification executed in the target logic circuit is simulated, and the logical operation of the instruction specification description information a is simulated. Confirmation, that is, verify logical validity.

Next, based on the instruction specification description information a and the instruction specification 5 whose logical validity is guaranteed, the test procedure and diagnosis procedure for testing and diagnosing the target logic circuit are set as the test diagnosis procedure description information. The test diagnosis procedure description information d is input to the diagnostic procedure input means 2, and the test diagnosis procedure description information d is converted into simulation model information d in a format that can be input to the simulation means 4. Then, the simulation model information d converted based on the instruction specification description information a whose logical validity is guaranteed and the simulation model information d output by the test diagnosis procedure input means 2,
By inputting the information to the simulation means 4, the test diagnosis procedure is simulated by the operation according to the instruction specifications, and the normal operation of the test diagnosis procedure description information is confirmed, that is, the validity is verified.

Next, based on the instruction specification description information a whose logical validity is guaranteed and the instruction specification 5, the functional configuration and logical operation of the target logic circuit that embodies the target logic circuit are defined as functional specification description information C. The functional specification description information C is input to the specification input means 3, and the functional specification description information C is converted into simulation model information d in a format that can be input to the simulation means 4, and the test diagnosis procedure is guaranteed to be valid. By inputting the simulation model information d converted based on the descriptive information and the simulation model information d output by the functional specification input means 3 into the simulation means 4, the functional configuration and logical operation can be determined by testing procedures and diagnostic procedures. A simulation is performed to confirm the logical functions and logical operations of the functional specification description information C, that is, to verify the logical validity.

〔Effect of the invention〕

As explained above, the present invention makes it possible to verify the logical validity of instruction specifications, the validity of test diagnostic procedure description information, and the logical validity of functional specifications using simulation means. This has the effect that the time required for designing and verifying large-scale logic circuits can be shortened, and that fewer media resources are required for this purpose.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 2 is a diagram showing a specific image of the logic circuit verification method shown in the figure. 1... Command specification input means, 2... Test diagnosis procedure input means, 3... Functional specification input means,
4. Simulation means for 5. Instruction specifications. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] In a logic circuit verification method for hardware design of large-scale logic circuits, (A) instruction specification description information expressing instruction specifications to be executed in a target logic circuit is input and is in a format that allows simulation. an instruction specification input means for creating simulation model information; (B) inputting test diagnosis procedure description information created for testing and diagnosing the target logic circuit, and creating simulation model information in a format that allows simulation; test diagnosis procedure input means; (C) functional specification input means for inputting functional specification description information expressing the function of the target logic circuit to create simulation model information in a format that allows simulation; (D) said simulation model information. A logic circuit verification method comprising: a simulation means for inputting and performing a simulation.